DS92UT16 Datasheet, PDF (30/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

DS92UT16
OBSOLETE
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
www.ti.com
ANALYZING LOCK AND SYNCHRONIZATION TIME
After the DS92UT16 LVDS receiver’s PLL locks onto the incoming serial data stream and begins to recover data,
it must achieve TC lock, then frame lock and descrambler lock before transferring cells. The number of cycles to
complete this synchronization depends on the PDU length as well as the byte location in the TC and frame
where the receiver begins synchronizing.
Here are the assumptions for this example on calculating the synchronization time.
• PDU length = 64 bytes (maximum possible) = 32 cycles (16 bit data path)
• Max TC length =PDU + 4 bytes = 34 cycles
• Frame = 56 TC = 1904 cycles
Once the LVDS Receive input PLL locks to the incoming serial data stream and recovers data bits, the
DS92UT16 searches for a TC HEC byte. Assuming that the DS92UT16 just missed a HEC when the LVDS PHY
locked, it will take a minimum of one TC to find the HEC byte. Next, the DS92UT16 will continue finding correct
TC HECs until it matches the number in the confidence counter (default setting is DELTA = 8). The TC
delineation is now in sync.
Next, the UT16 will start looking for SOF HECs that indicate a start-of-frame. Assuming a SOF has just passed,
the max time to find an SOF should be 1 Frame. Now the UT16 will collect frames until the correct number
matches the confidence counter (default setting is SIGMA = 8). When the correct number of SOFs matches the
confidence counter, the frame delineation is in sync.
Simultaneous with the frame delineation, the DS92UT16 will synchronize and lock the descrambler. The lock
procedure begins with the transmitting DS92UT16 sending the scrambler sequence in idle cells. It does this
automatically on reset or start-up until it receives the cleared RDSLL bit in the Remote Alarm and Signaling byte.
After TC delineation occurs at the receive end, the DS92UT16 will count correct scrambler sequence predictions
until it matches the confidence counter (default setting is RHO = 8). When the correct number of scrambler
sequence predictions matches the confidence counter, the descrambler is synchronized and the receiving
DS92UT16 clears the RDSLL bit.
In this example, the time it takes for a receiving DS92UT16 to synchronize to the transmitting DS92UT16, after
the PLL locks, is approximately determined by the following calculation. This time will differ according to PDU
length and the value programmed as the confidence thresholds.
(1+8) TC = 9 (34 cycles) = 306 cycles for TC sync, and (1+8) (1 frame) = 9 (1904 cycles) = 17136 cycles. This is
a total of 17442 cycles and assumes that the descrambler lock occurs during the 8 frames it takes for the frame
delineation to occur.
LVDS Interface Operation
The LVDS interface combines a transmit serializer and two receive deserializers. The serializer accepts 16- bit
data from the TCS Assembler block and transforms it into a serial data stream with embedded clock information.
Each deserializer recovers the clock and data from the received serial data stream to deliver the resulting 16-bit
wide words to the corresponding TCS DisAssembler block.
The LVDS interface has a Transmit serializer block and two Receive deserializer blocks that can operate
independent of each other. The transmit data is duplicated over two differential output pairs with independent tri-
state controls. The transmit block has a power-down control. Each receiver has a power down control and the
two output stages have independent tri-state control. These features enable efficient operation in various
applications.
The serializer and deserializer blocks each have three operating states. They are the Initialization, Data Transfer,
and Resynchronization states. In addition, there are two passive states: Powerdown and TRI-STATE.
The following sections describe each operating mode and passive state. For clarity these descriptions refer only
to the receive Port A. The operation of receive Port B is the same.
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