DS92UT16 Datasheet, PDF (102/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

DS92UT16
OBSOLETE
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
SUPPLY CURRENT, V_CC = 3.3V
Over recommended operating supply and temperature ranges unless otherwise specified.⁽¹⁾
Symbol
Parameter
Conditions
Pin/Freq.
Min
I_CCR
Worst Case Supply Current Utopia C_L = 15 pF, Bus
LVDS R_L = 100Ω, Checker
Pattern, VDD = 3.6V
52 MHz
I_CCT
Typical Loading and
Switching
C_L = 15 pF, PRBS7 Data
Pattern
33 MHz
(1) Typical values are given for V_CC = 3.3V and T_A = 25°C
UTOPIA BUS SWITCHING CHARACTERISTICS
Over recommended operating supply and temperature ranges unless otherwise specified.⁽¹⁾
Symbol
Parameter
Conditions
Pin/Freq.
Min
t_UCP
Input Clock Period
t_UDC
Input Clock Duty Cycle
t_UJIT
Input Clock Jitter
20
U_UUBClk,
U_UDBClk
40
t_USETUP Input Data Valid before CLK C_L = 30 pF (see Figure 31)
Inputs
4
t_UHOLD
Input Data Valid after CLK C_L = 30 pF (see Figure 31)
1
t_ULH
Output Low-to-High
Transition Time
C_L = 30 pF (see Figure 31)
1
t_UHL
Output High-to-Low
Transition Time
C_L = 30 pF (see Figure 31)
1
t_UROS
Output Data Valid before
CLK
C_L = 30 pF (see Figure 31)
4
Outputs
t_UROH
Output Data Valid after CLK C_L = 30 pF (see Figure 31)
1
t_UHZR
High to TRI-STATE Delay
1
t_ULZR
Low to TRI-STATE Delay
(See Figure 32)
1
t_UZHR
TRI-STATE to High Delay
1
t_UZLR
TRI-STATE to Low Delay
1
(1) Typical values are given for V_CC = 3.3V and T_A = 25°C
U_TxData[15:0]
U_Tx Parity
U_Tx CLAV[7:4]
U_TxCLAV[3:0]
U_TxENB[7:1]
U_TxENB[0]
U_TxSOC
U_TxAddr[4:0]
U_RxData[15:0]
U_Rx Parity
U_Rx CLAV[7:4]
U_RxCLAV[3:0]
U_RxENB[7:1]
U_RxENB[0]
U_RxSOC
U_RxAddr[4:0]
Pin Name
ATM Mode
Output
Output
Input
Input
Output
Output
Output
Output
Input
Input
Input
Input
Output
Output
Input
Output
(1) The extended addressing pins U_TxCLAV[7:4], U_RxCLAV[7:4], U_TxENB[7:1], and
U_RxENB[7:1] are defined for ATM mode only.
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Typ Max Units
270
360 mA
140
165 mA
Typ Max Units
ns
50
60
%
1
5
%
ns
ns
8
ns
8
ns
ns
ns
16
ns
16
ns
16
ns
16
ns
PHY Mode
Input
Input
See ⁽¹⁾
Output
See ⁽¹⁾
Input
Input
Input
Output
Output
See ⁽¹⁾
Output
See ⁽¹⁾
Input
Output
Input
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