DS92UT16 Datasheet, PDF (69/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

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DS92UT16
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SNOS992E – JANUARY 2002 – REVISED APRIL 2013
RECEIVE PORT A BIP THRESHOLD—0x36 to 0x39 RABIPT2 to RABIPT0
Table 49. RABIPT2–RABIPT0
7
RABIPT2
0x37
RABIPT2[7]
RABIPT1
0x38
RABIPT1[7]
RABIPT0
0x39
RABIPT0[7]
Type: Read/Write
6
RABIPT2[6]
RABIPT1[6]
RABIPT0[6]
5
RABIPT2[5]
RABIPT1[5]
RABIPT0[5]
4
RABIPT2[4]
RABIPT1[4]
RABIPT0[4]
3
RABIPT2[3]
RABIPT1[3]
RABIPT0[3]
2
RABIPT2[2]
RABIPT1[2]
RABIPT0[2]
1
RABIPT2[1]
RABIPT1[1]
RABIPT0[1]
0
RABIPT2[0]
RABIPT1[0]
RABIPT0[0]
Software Lock: No
Reset Value: 0xFF
The RABIPT2, RABIPT1 and RABIPT0 registers contain the Port A received errored BIP threshold. When the
error count RABIPC equals the threshold RABIPT then the RAXBIP alarm will be set.
These registers should not be set to all zeroes.
• RABIPT2–RABIPT0 Most significant byte RABIPT2 and least significant byte RABIPT0.
RECEIVE PORT A PERFORMANCE ALARMS—0x3A RAPA
Table 50. RAPA
7
6
Reserved Reserved
Type: Read only/Clear on Read
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
RAXHEC
0
RAXBIP
Software Lock: No
Reset Value: 0x00
The Receive Port A Performance Alarms register contains information about the error performance of Port A.
When set RAXHEC and RAXBIP will raise an interrupt if the corresponding interrupt enable bits are set.
• RAXHEC Receive Port A, Excessive HEC Errors. Set = Number of HEC errors counted in RAHECC is equal
to or greater than the threshold set in RAHECT. This bit is set when RAHECC = RAHECT and can only be
cleared by a read of this register.
• RAXBIP Receive Port A, Excessive BIP Errors. Set = Number of BIP errors counted in RABIPC is equal to or
greater than the threshold set in RABIPT. This bit is set when RABIPC = RABIPT and can only be cleared by
a read of this register.
RECEIVE PORT A PERFORMANCE INTERRUPT ENABLES—0x3B RAPIE
Table 51. RAPIE
7
Reserved
Type: Read/Write
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
1
0
Reserved RAXHECIE RAXBIPIE
Software Lock: No
Reset Value: 0x00
This register contains the interrupt enables for the alarms in the RAPA register. Set = interrupt enabled and Clear
= interrupt disabled.
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