DS92UT16 Datasheet, PDF (49/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

OBSOLETE
DS92UT16
www.ti.com
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
Register Description
This section describes all the software accessible registers in the DS92UT16. A summary of all registers is
shown in Table 19.
Register Name
SLK0
SLK1
VID
GCS
LVC
PDUCFG
IS
ISE
LKSC
TXLL
ETXRXA
ETXRXIE
ETXSD
ETXD7
ETXD6
ETXD5
ETXD4
ETXD3
ETXD2
ETXD1
ETXD0
GPIO
TERRCTL
ERRBIP1
ERRBIP0
ERRHEC
ALBC
ALBMP
ALBCF3
ALBCF2
ALBCF1
ALBCF0
RALL
RAELL
RALA
RALIE
RACTL
Reserved
ERAD7
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
Table 19. Register Map Summary^(1)(2)(3)
Software
Lock
N
N
N
Y
Y
Y
N
N
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
Y
Reset
Value
0x00
0x00
See ⁽⁴⁾
0x05
0x3B
0x00
0x00
0x00
0x34
0x00
0x01
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xF0
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x01
Section and Description
18.1 Software Lock 1
18.1 Software Lock 2
18.2 Version Identification
18.3 General Control and Status
18.4 LVDS Control
18.5 PDU Configuration
18.6 Interrupt Source
18.7 Interrupt Source Enables
18.8 Link Status and Control
18.9 Transmit Link Label
18.10 ECC Transmit Buffer and Receive LVDS Alarms
18.11 ECC Transmit Buffer and Receive LVDS Interrupt Enables
18.12 ECC Transmit Buffer Send
18.13 ECC Transmit Buffer 7
18.13 ECC Transmit Buffer 6
18.13 ECC Transmit Buffer 5
18.13 ECC Transmit Buffer 4
18.13 ECC Transmit Buffer 3
18.13 ECC Transmit Buffer 2
18.13 ECC Transmit Buffer 1
18.13 ECC Transmit Buffer 0
18.14 General Purpose Input/Output
18.15 Test Error Control
18.16 BIP Error Mask 1
18.16 BIP Error Mask 0
18.17 HEC Error Mask 0
18.18 ATM and LVDS Loopback Control
18.19 ATM Loopback Cell MPhy
18.20 ATM Loopback Cell Format 3
18.20 ATM Loopback Cell Format 2
18.20 ATM Loopback Cell Format 1
18.20 ATM Loopback Cell Format 0
18.21 Receive Port A Link Label
18.22 Receive Port A Expected Link Label
18.23 Receive Port A Local Alarms
18.24 Receive Port A Local Interrupt Enables
18.25 Receive Port A Control
N
0x00 18.26 ECC Receive Buffer A 7
(1) All configuration and control registers can be read by the processor to determine the status of the DS92UT16.
(2) All reserved (register bits for internal use only) and unused (no register) bits will be read as zero and should be written as zero to ensure
future compatibility.
(3) Writing to read only register bits has no affect.
(4) The reset value of the VID register will be different for various versions of the device.
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