DS92UT16 Datasheet, PDF (11/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

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DS92UT16
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SNOS992E – JANUARY 2002 – REVISED APRIL 2013
The status of the received RLOSA, RLOSB, RBA and RDSSL bits is reflected in the RARA register for receive
port A and in RBRA for receive port B. See RECEIVE PORT A REMOTE STATUS AND ALARMS—0x3C RARA
and RECEIVE PORT B REMOTE STATUS AND ALARMS—0x7C RBRA for descriptions of these registers.
The function of the ECC signaling bits EVN, ESSA, and ESSB is described in Embedded Communication
Channel Operation.
Link Trace Label Byte
Also, in TC6 a byte-wide link trace label is carried in the F2 byte as shown in F Channel Byte Usage Within the
Frame. This allows the user to verify link connectivity, which is especially useful when a number of cable links
are being used. The DS92UT16 may be programmed with both a link label value to transmit and an expected link
label. Should the received link label not match the expected value, an alarm interrupt may be raised.
The received Link Label byte is software accessible and an interrupt may be raised on a change of received Link
Label byte. So the Link Label byte may also be used as a user defined channel to pass one byte per frame
across the link.
Embedded Communications Channel (ECC)
An Embedded Communications Channel is provided over the link for software messaging, download, etc. in the
F1/F2 bytes of TCs 13, 20, 41 and 48 as shown in Table 4. The ECC byte contents are not processed by the
DS92UT16. Hence the DS92UT16 is transparent to and does not restrict the system messaging protocol.
The ECC consists of an 8 byte Tx Buffer with corresponding Tx Buffer Ready and Tx Buffer Send flags, and an 8
byte Rx Buffer with a corresponding Rx Buffer Full Flag. All bytes of the buffers are software read/write
accessible. Tx Buffer Ready is read only.
At the ECC transmit side, the reset state sets the Tx Buffer Ready flag and clears the Tx Buffer Send flag. Then
the software assembles a message for transmission in the Tx Buffer. To send a message, the software simply
sets Tx Buffer Send, which automatically clears Tx Buffer Ready. The contents of the Tx Buffer are transmitted to
the far-end. The Tx Buffer will automatically be retransmitted until the far-end indicates that it has been
successfully received. When notified by the far end of successful reception, Tx Buffer Ready is set and an
interrupt raised to the software to indicate successful transmission. A new message may now be assembled in
the Tx Buffer and transmitted by setting Tx Buffer Send. As all the Tx Buffer bytes are read/ write, the message
to be transmitted can be assembled in any order and read back by the software before transmission. The same
message can be retransmitted simply by setting Tx Buffer Send again.
At the ECC receive side, the reset state clears the Rx Buffer Full flag. When all 8 bytes of a message have been
successfully received and stored in the Rx Buffer, the Rx Buffer Full flag is set and an interrupt raised. As all the
Rx Buffer bytes are read/write, the message can be read in any order by the software. A new message will not
overwrite the current received message until the Rx Buffer Full flag is cleared by the software indicating that the
current Rx Buffer has been read and a new message can be received.
The ECC data flow is controlled across the link using the EVN, ESSA, and ESSB bits of the Remote Alarm and
Signaling byte (see Remote Alarm and Signaling Byte).
As there are two independent LVDS receive ports, the DS92UT16 has two independent ECC receive sections.
These are assigned to the LVDS receive ports Port A and Port B. The ECC of the standby link may therefore be
used for software communication.
Embedded Communication Channel Operation describes the operation and control of the ECC in detail.
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