DS92UT16 Datasheet, PDF (78/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

DS92UT16
OBSOLETE
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
RECEIVE PORT B PERFORMANCE ALARMS—0x7A RBPA
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Table 69. RBPA
7
6
Reserved Reserved
Type: Read only/Clear on Read
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
RBXHEC
0
RBXBIP
Software Lock: No
Reset Value: 0x00
The Receive Port B Performance Alarms register contains information about the error performance of Port B.
When set RBXHEC and RBXBIP will raise an interrupt if the corresponding interrupt enable bits are set.
• RBXHEC Receive Port B, Excessive HEC Errors. Set = Number of HEC errors counted in RBHECC is equal
to or greater than the threshold set in RBHECT. This bit is set when RBHECC = RBHECT and can only be
cleared by a read of this register.
• RBXBIP Receive Port B, Excessive BIP Errors. Set = Number of BIP errors counted in RBBIPC is equal to or
greater than the threshold set in RBBIPT. This bit is set when RBBIPC = RBBIPT and can only be cleared by
a read of this register.
RECEIVE PORT B PERFORMANCE INTERRUPT ENABLES—0x7B RBPIE
Table 70. RBPIE
7
Reserved
Type: Read/Write
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
1
0
Reserved RBXHECIE RBXBIPIE
Software Lock: No
Reset Value: 0x00
This register contains the interrupt enables for the alarms in the RBPA register. Set = interrupt enabled and Clear
= interrupt disabled.
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