DS92UT16 Datasheet, PDF (3/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

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Application Overview
OBSOLETE
DS92UT16
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
Figure 2. Application Example
The UTOPIA interface [See References] is an established standard for connecting Physical Layer devices to
ATM Layer devices. However, when the ATM Layer device and the Physical Layer device(s) are on separate
cards within a piece of equipment, or even on separate equipment, then the parallel nature of this standard
becomes a limiting factor. See Figure 2.
The solution is to use the DS92UT16, which is a transparent bridge that extends the UTOPIA bus over a serial
LVDS interface, and is suitable for backplanes and cables. Full bidirectional flow control is incorporated, allowing
back-pressure to be applied to the source of the ATM cells. The 31 PHY ports available with standard UTOPIA
Level 2 may be extended to 248 ports without additional external circuitry. The DS92UT16 achieves this by
providing as many as 8 ENB and CLAV signals in both receive and transmit directions when acting as the ATM
Layer device. This allows addressing 248 PHYs that are configured as up to 31 ports that each have as many as
8 sub-ports.
To aid equipment management and maintenance, the DS92UT16 passes an embedded ‘Operations,
Administration and Maintenance' (OAM) channel over the serial link. In addition, the device provides a number of
loopback options that are both traffic affecting (line loopbacks) and non-traffic affecting (cell loopbacks), which
simplify testing and diagnostic activities.
The DS92UT16 has a modified Bus LVDS serial output for driving cables in point-to-point applications. The cable
length depends on the quality of the cable and the data rate. Increasing the cable quality, or lowering the LVDS
data rate, increases the maximum possible cable length the device will drive.
When examining the trade-offs that determine the DS92UT16 maximum cable drive capability, it is important to
understand that the LVDS data rate on the cable is 18 times (16 bits plus 2 embedded clock bits) the
LVDS_TxClk rate. For example, a 35 MHz LVDS_TxClk will produce a 630 Mbps data rate, and a 52 MHz clock
will produce a 936 Mbps data rate. When using twinaxial grade differential cable, the cable length can be as long
as 16m for the 35 MHz clock and approximately 10m for the 52 MHz clock.
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