DS92UT16 Datasheet, PDF (13/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

OBSOLETE
DS92UT16
www.ti.com
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
Table 8. F Channel Bandwidth—Percentage
Link BW - Mbps
Container Size - Bytes
Remote Alarm BW%
Link Label BW%
ECC BW%
Reserved BW%
BIP16 BW%
OAM BW%
Flow Control BW%
F Channel BW%
800
800
56
68
0.03
0.03
0.03
0.03
0.26
0.21
0.06
0.05
0.13
0.10
0.51
0.42
3.06
2.52
3.57
2.94
LVDS PHYSICAL INTERFACE
The DS92UT16 provides one dual transmit and two independent receive high speed LVDS serial interfaces with
800 Mbps bandwidth. The LVDS Interface transmits and receives data over lightly loaded backplanes or up to
10m of cable. The single transmit block drives two pairs of differential outputs with independent TRI-STATE
controls for each. The same data is transmitted over both pairs of transmit pins. The two serial receive interfaces
are completely separate and independent and are denoted Port A and Port B. Only one receive port is selected
for traffic at any one time. This is designated the Active Port. The Standby receive port may be powered down.
Alternatively, the Standby receive port’s OAM channel can be made available for software communications using
the ECC, and for link performance monitoring. This allows the condition of the Standby link to be determined.
The LOCK status of both Active and Standby ports is monitored automatically.
The transmitted data stream contains embedded clock information. The receiver’s clock recovery circuit locks
onto the embedded clock in either a random data pattern, or by instructing the transmitter to send SYNCH
patterns. The DS92LV16 can send SYNCH patterns on power-up or when synchronization is lost. The latter
option requires a feedback loop in either hardware or software between the transmitter and the receiver, but has
the benefit of a faster lock time. The LOCK status of both receive ports is reflected on external pins and
alarm/status bits that are readable via the microprocessor port. The LOCK status, along with the currently active
port, is transmitted to the far-end receiver via the Remote Alarm and Signaling byte of the OAM channel as
described in Remote Alarm and Signaling Byte. The recovered clocks of both receive ports are available on
external pins.
A Loop Timing option is available whereby the LVDS transmit clock can be sourced directly from the recovered
clock of the active receiver, rather than from the external transmit clock input pin.
The transmit port and two receive ports may be independently powered down via microprocessor control.
Similarly, the device may be forced to send SYNCH patterns on the transmit port via microprocessor control.
To assist in designer testing and system commissioning of the LVDS interface, the DS92UT16 has a built in BER
test facility. The device may be configured to send a PRBS pattern in place of ATM cells. At the receiver, the
device locks onto this PRBS pattern and provides an error metric.
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: DS92UT16
Submit Documentation Feedback
13