DS92UT16 Datasheet, PDF (107/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

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OBSOLETE
DS92UT16
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
APPENDIX A: LAYOUT AND CONNECTION GUIDELINES
Figure 33. Block Diagram Is a Top View of 196 LBGA Ball Assignment.
POWER CONNECTIONS
Digital Supplies (DV_DD and DGND)
The digital supply pins provide power to the digital section of the device. Since the digital supplies are subject to
switching noise, the bypass considerations are important. The DV_DD and DGND balls are located mostly in the
center of the ball array. If the PCB stack-up and signal routing allows placing bypass caps on the bottom of the
board close to the digital supply pins, then an array of capacitors will provide wide band bypassing. The total
bypass capacitance should be at least 0.3 µF.
The 2.5V supply pins are located near the edge of the package, which is more convenient for placement of
bypass capacitors. If a power plane supplies the 2.5V, then standard bypass capacitors of 0.1 µF in parallel with
0.01 µF is sufficient. If the PCB traces connect the 2.5V to the part, then additional bulk decoupling capacitance
should account for the added trace inductance.
Analog Supplies (AV_DD and AGND)
The analog V_DD and GND power the LVDS driver and receiver section of the device. High frequency bypassing
such as 0.001 µF capacitance is required due to the very high data rates of the LVDS signals. See Figure 34.
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