DS92UT16 Datasheet, PDF (34/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

DS92UT16
OBSOLETE
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
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NOTE
From the time that the near end device is switched to or from Loop Timing mode, until the
time that the far end device registers the loss of scrambler lock, all received data at the far
end will be corrupted. This is because the scrambler lock works on a frame-by-frame basis
and each frame is 56 transport containers long. For this reason switching to or from Loop
Timing mode should not be carried out on live traffic.
NOTE
Both the input LVDS_TxClk clock and active port recovered clock must be present for the
switch to complete successfully.
NOTE
On reset the device will operate from the LVDS_TxClk input pin clock and therefore this
clock must be present to ensure correct operation.
Switching Receive Ports
The DS92UT16 has two independent receive sections designated Port A and Port B. Either port can receive
ATM cell traffic, but only one at a time. The LBA bit of the LKSC register, described in LINK STATUS AND
CONTROL—0x08 LKSC, controls this function.
The ECC also has two independent receive sections. This is controlled by the settings of the ECCA and ECCB
bits of the LKSC register. Either one or both ECC receive sections can be active. The selected ECC receive port
is independent of the active traffic port selection. For example, you may select Port A as active for cell traffic by
clearing the LBA bit, and select the ECC to be receiving on Port B by setting the ECCB bit. The ECC can
communicate over either link without affecting the active cell traffic port because the ECC does not use any of
the transport container designated for ATM cells.
Selecting the active traffic receive port is accomplished by simply changing the value of the LBA bit. When set
high, Port B accepts the traffic cells, and when cleared to low, Port A accepts the traffic cells. After changing the
LBA value, the MTB will complete receiving the current cell before switching to the new receive Port. The MTB
then waits for the next Start of Cell indication from the associated TCS DisAssembler. This means that the MTB
does not need to be flushed or reset because of a change in the active traffic receive Port.
Switching from one port to another completes in a maximum of 6 clock cycles. However, this switch does not
start until after receiving the end of the current cell into the MTB.
Changing the value of the LBA bit to switch ports will clear the ABSC bit of the LKSC register. When the switch
from one port to the other is completed successfully then the hardware will set the ABSC bit. The processor can
poll this bit to determine when the switch has been completed.
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