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DS92UT16 Datasheet, PDF (40/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers
DS92UT16
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
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Figure 15. The Basic Structure Of The ECC
BASIC ECC PROTOCOL—ONE TRANSMIT AND ONE RECEIVE
The basic operation of an ECC link is described here using the transmit section of the device at one end of the
LVDS link and a single receive section (Port A) of the device at the other end of the link.
The ECC transmitter and receiver communicate via the embedded control signals EVN, ESSA and ESSB in the
Remote Alarm and Signaling byte contained in the F1 byte of TC6. By default both receive ports will extract the
incoming ESSA bit as the valid ESS to pass to the ECC transmit section. This assumes that the local ECC
transmit section is connected to the remote device receiver port A. If the local transmitter is connected to the
remote device receiver port B then the incoming ESSB bit must be selected as the valid ESS to pass to the local
ECC transmit section. The selection of valid incoming ESS bit is accomplished using the RAESS and RBESS
bits of the RACTL and RBCTL registers respectively.
Note that only one of the incoming remote ESS bits is valid on each link as the local transmitter cannot be
connected to both receivers on another DS92UT16 device.
The EVN and ESS bits are interpreted as follows:
EVN - Set = Valid ECC data in F1/F2 bytes of TC13, TC20, TC41 and TC48.
Clear = Null (not valid) ECC data in F1/F2 bytes of TC13, TC20, TC41 and TC48.
ESS - Set = Stop sending ECC data as receive buffer is full.
Clear = Send ECC data as receive buffer is ready.
The protocol for transmission of an ECC message is as follows.
Reset
The transmit buffer ready ETXBR bit is set indicating that the transmit buffer ETXD7–ETXD0 can be written to
and the Tx Buffer Freeze is clear (inactive).
The transmit buffer send ETXSD bit is clear indicating that no message is being sent and therefore EVN is clear
indicating to the receiver that Null data is being transmitted.
The receive buffer full ERABF bit is clear indicating that no message has been received and therefore ESS is
clear indicating to the transmitter that it can send a message when ready.
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