DS92UT16 Datasheet, PDF (84/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

DS92UT16
OBSOLETE
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
UTOPIA SUB-PORT ADDRESS MASK—0xA8 USPAM
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Table 82. USPAM
7
USPAM[7]
Type: Read/Write
6
USPAM[6]
5
USPAM[5]
4
USPAM[4]
3
USPAM[3]
2
USPAM[2]
1
USPAM[1]
0
USPAM[0]
Software Lock: Yes
Reset Value: 0x07
The UTOPIA Sub-Port Address Mask register defines which bits of the PDU header byte defined by the USPAL
register contain the sub-port address.
• USPAM[7:0] Set = This bit location contains valid sub-port address bit.Clear = Ignore this bit location.
Note that only 3 bit locations must be set in this register to give the 3 bit sub-port address location. All other bits
must be clear. By default, bits USPAM[2:0] are set, indicating that the sub-port address is located in bits [2:0] of
the PDU header byte indicated by the USPAL register, with the MSB in bit [2] and the LSB in bit [0]. If USPAM
bits [6], [4] and [1] were set, then the sub-port address would be located in bits [6], [4] and [1] of the PDU header
byte indicated by the USPAL register, with the MSB in bit [6] and the LSB in bit [1].
MTB QUEUE THRESHOLD—0xA9 to 0xC7 MTBQT30 to MTBQT0
Table 83. MTBQT30–MTBQT0
7
MTBQT30
0xA9
MTBQT30[7]
MTBQT29
0xAA
MTBQT29[7]
MTBQT2
0xC5
MTBQT2[7]
MTBQT1
0xC6
MTBQT1[7]
MTBQT0
0xC7
MTBQT0[7]
Type: Read/Write
6
MTBQT30[6]
MTBQT29[6]
MTBQT2[6]
MTBQT1[6]
MTBQT0[6]
5
MTBQT30[5]
MTBQT29[5]
MTBQT2[5]
MTBQT1[5]
MTBQT0[5]
4
MTBQT30[4]
MTBQT29[4]
MTBQT2[4]
MTBQT1[4]
MTBQT0[4]
3
MTBQT30[3]
MTBQT29[3]
MTBQT2[3]
MTBQT1[3]
MTBQT0[3]
2
MTBQT30[2]
MTBQT29[2]
MTBQT2[2]
MTBQT1[2]
MTBQT0[2]
1
MTBQT30[1]
MTBQT29[1]
MTBQT2[1]
MTBQT1[1]
MTBQT0[1]
0
MTBQT30[0]
MTBQT29[0]
MTBQT2[0]
MTBQT1[0]
MTBQT0[0]
Software Lock: Yes
Reset Value: 0x04
The MTB Queue Threshold registers define the maximum size, in PDU cells, of each of the 31 queues. If all 31
queues are being used, it is recommended that the threshold be left at the default of 4 cells. If less than 31
queues are in use, then the queue threshold may be raised according to SINGLE BRIDGE MTB
CONFIGURATION.
• MTBQT30[7:0] Maximum number of PDU cells for queue 30.
• MTBQT29[7:0] Maximum number of PDU cells for queue 29.
• ...................
• MTBQT1[7:0] Maximum number of PDU cells for queue 1.
• MTBQT0[7:0] Maximum number of PDU cells for queue 0.
84
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