DS92UT16 Datasheet, PDF (17/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

OBSOLETE
DS92UT16
www.ti.com
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
PIN DESCRIPTION (continued)
Signal Name
Description
CPU & GENERAL CONTROL
CPU_cs
Select signal used to validate the address bus for
read and write data transfers.
CPU_rd (CPU_ds)
Read or Data Strobe, depending on CPU_BusMode.
CPU_wr (CPU_rnw) Write or Read/Write, depending on CPU_BusMode.
Width
1
1
1
CPU_int
Interrupt request line.
1
CPU_Data[7:0]
Data bus.
8
CPU_Addr[7:0]
Address bus.
8
CPU_BusMode
Mode select for bus protocol.
1
GPIO [3:0]
General Purpose Input/Output.
4
Reset_n
Reset min pulse is 2X slowest clock period.
1
JTAG TEST INTERFACE
JTAG_CLK
Test clock.
1
JTAG_Reset
Test circuit reset.
1
JTAG_TMS
Test Mode Select.
1
JTAG_TDI
Test Data In.
1
JTAG_TDO
Test Data Out.
1
Test_se
SCAN enable (for manufacturing test only)
1
TOTAL PIN COUNT
Total Functional I/O
LVDS V_DD/V_SS
CV_DD/CV_SS
IOV_DD/IOV_SS
Total Power
3.3V LVDS power for analog and digital
2.5V Core Power for digital functions
3.3V I/O power ring
No Connect
No signal connected to this pin
Total Pins
196 LBGA, 15x15 mm, 1.0 mm ball pitch
Signal Type
Polarity
Input
Input
Input
Output
BiDir
Input
Input
BiDir
Input
Active Low
Active Low
Active Low
(Write)
Active Low
Active Low
Input
Input
Input
Input
Output
Input
Active Low
Active High
133
46
6
8
60
3
196
Internal
Bias
Open Drain
Pull Down
Pull Up
Pull Up
Pull Up
Pull Down
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