DS92UT16 Datasheet, PDF (35/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

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DS92UT16
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Performance Monitoring
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
LIVE TRAFFIC PERFORMANCE MONITORING
Performance monitoring is carried out on live traffic in two ways. One is using the HEC bytes associated with
each cell’s TC. The other is the BIP bytes of the F channel embedded in the frame structure, as described in
BIP16.
A 24-bit count of errored HEC’s received on Port A is contained in the RAHECC2–RAHECC0 registers (see
RECEIVE PORT A HEC COUNT—0x2E to 0x30 RAHECC2 to RAHECC0). When the number of received erred
HEC’s exceeds the threshold defined in the RAHECT2–RAHECT0 registers (see RECEIVE PORT A HEC
THRESHOLD—0x31 to 0x33 RAHECT2 to RAHECT0), an interrupt may be raised on the RAXHEC alarm bit in
the RAPA alarm register (see RECEIVE PORT A PERFORMANCE ALARMS—0x3A RAPA). The count register
RAHECC2–RAHECC0 is reset on read.
A 24-bit count of errored BIP bytes is similarly maintained in the RABIPC2–RABIPC0 registers (see RECEIVE
PORT A BIP COUNT—0x34 to 0x36 RABIPC2 to RABIPC0). The associated erred BIP threshold is contained in
the RABIPT2–RABIPT0 registers (see RECEIVE PORT A BIP THRESHOLD—0x36 to 0x39 RABIPT2 to
RABIPT0) and an interrupt may be raised on the RAXBIP alarm bit in the RAPA alarm register. The count
register RABIPC2–RABIPC0 is also reset on read.
The same mechanism is in place for Port B using the RBHECC2–RBHECC0, RBHECT2–RBHECT0, RBBIPC2–
RBBIPC0, RBBIPT2–RBBIPT0 and RBPA registers (see RECEIVE PORT B HEC COUNT—0x6E to 0x70
RBHECC2 to RBHECC0, RECEIVE PORT B HEC THRESHOLD—0x71 to 0x73 RBHECT2 to RBHECT0,
RECEIVE PORT B BIP COUNT—0x74 to 0x76 RBBIPC2 to RBBIPC0, RECEIVE PORT B BIP
THRESHOLD—0x77 to 0x79 RBBIPT2 to RBBIPT0 and RECEIVE PORT B PERFORMANCE ALARMS—0x7A
RBPA).
In addition to the HEC and BIP monitoring, live traffic loopback cell monitoring and loopback cell counts are
maintained and may raise interrupts on detection of a loopback cell as described in ATM CELL LOOPBACK.
BIT ERROR COUNT MODE
In addition to live traffic performance monitoring, a PRBS based LVDS link bit error count facility is available. In
this mode, no cells are transmitted and instead the raw scrambler pseudo-random sequence (polynomial x³¹ +
x²⁸ + 1) is transmitted. The descrambler will lock to this sequence and then count individual bit errors in the
PRBS stream. This bit error count is maintained in a count register. As there is no data cell delineation, the frame
delineation will be lost. This is not a live traffic test.
The device will transmit this PRBS data when the TXPRBS bit of the TERRCTL register is set (see TEST
ERROR CONTROL—0x16 TERRCTL). When this bit is set, no cell data is transmitted and the TCS Assembler is
paused. In addition, no cells will be read from the FIB queue.
The receive section of Port A can lock onto this sequence and maintain the bit error count when the RABEC bit
of the RACTL register is set (see RECEIVE PORT A CONTROL—0x24 RACTL). The bit error count is
maintained in the RABEC2–RABEC0 registers (see RECEIVE PORT A BIT ERROR COUNT—0x43 to 0x45
RABEC2 to RABEC0). This counter has no associated threshold register and will not generate an interrupt. The
counter may be polled (read) at fixed intervals to determine a Bit Error Rate. This counter is reset on read. The
count value is only valid when both the TXPRBS bit and the RABEC bit are set.
Port B can operate in the same fashion using the RBBEC bit of the RBCTL register (RECEIVE PORT B
CONTROL—0x64 RBCTL) and the RBBEC2–RBBEC0 registers (see RECEIVE PORT B BIT ERROR
COUNT—0x83 to 0x85 RBBEC2 to RBBEC0).
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