DS92UT16 Datasheet, PDF (108/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

DS92UT16
OBSOLETE
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
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PLL Supplies (PV_DD and PGND)
The PLL supply pins provide power for the PLL(s) in the circuit. The most important function of bypassing or
filtering for the PLL inputs is to attenuate low frequency noise from entering the PV_DD pins. A common source of
low frequency noise is switching power supplies. Power distribution networks should be designed to attenuate
any harmonics created by the switching supply. The addition of a PI filter network at the PV_DD pins is optional.
See Figure 34.
LAYOUT GUIDELINES
Digital Supplies (DV_DD and DGND)
Digital supply connection to bypass capacitors can be difficult, but the more layers in the PCB the easier it is to
place the capacitors near the device. Therefore, the recommendation is to use full power planes to distribute
power to these pins. Using the minimum manufacturing thickness between the ground and power planes creates
a distributed bypass capacitance. Due to the potentially high inrush currents caused by Utopia bus output
switching, using traces routed through the array to connect bypass caps to the balls is not recommended. This is
because the inductance of the traces will negate the affect of the bypass capacitors.
Analog Supplies (AV_DD and AGND)
In general, the analog supply pins can be connected to the digital power planes. The AGND pins should be
connected to a ground plane that connects them directly to the AGND pins of the sending device. This provides
for minimum ground offset between the devices and provides a return path for the minute return currents from
the LVDS receivers.
PLL Supplies (PV_DD and PGND)
The PLL supply pins should be isolated from the shared digital and analog power planes. PV_DD and PGND pins
are generally grouped together to allow them to be connected to a split plane or to a “copper pour” on the top
layer. The split plane or copper pour is connected to the power planes through a PI filter to block low frequency
noise. High frequency bypassing should be provided on the PLL side of the filter to supply switching current to
the PLL. A separate filter for each PLL is recommended. If filters are not desired use a high value (5 µF to 400
nF) capacitor connected to the PV_DD pins to limit low frequency noise.
LVDS I/O
The LVDS I/O pins are located on the outer ring of balls so they can be routed on the surface layer to minimize
added capacitance. Use surface mount resistors to terminate transmission lines as close to the LVDS inputs as
possible. The LVDS drivers on the DS92UT16 are designed to drive 100Ω differential lines.
The LVDS A driver outputs (LVDS_Adin[+/−]) are swapped in position compared to the other LVDS I/O pairs.
This allows them to be “wrapped around ” a connector pin array so that all of the LVDS signals can be routed on
the surface layer. See Figure 35.
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