DS92UT16 Datasheet, PDF (33/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

OBSOLETE
DS92UT16
www.ti.com
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
POWERDOWN/TRI-STATE
The Powerdown state is a very low power consuming sleep mode that the Serializer and Deserializer will occupy
while waiting for initialization. You can also use the LVDS_ADenb, LVDS_BDenb, LVDS_TxPwdn, LVDS_APwdn
and LVDS_BPwdn pins, or the TXPWDN, TXADEN, TXBDEN, RAPWDN and RBPWDN bits of the LVC register
to reduce power when there are no pending data transfers. The Port A Deserializer enters Powerdown when
LVDS_APwdn is driven low or the RAPWDN bit is set. In Powerdown, the PLL stops and the outputs go into TRI-
STATE, which reduces supply current to the µA range.
To bring the Port A Deserializer block out of the Powerdown state, the system drives LVDS_APwdn high and the
RAPWDN bit is cleared. When the Deserializer exits Powerdown, it automatically enters the Initialization state.
The system must then allow time for Initialization before data transfer can begin.
The LVDS_TxPwdn driven low or the TXPWDN bit clear, forces the Serializer block into low power consumption
where the supply current is in the µA range. The Serializer PLL stops and the output goes into a TRI-STATE
condition.
To bring the Serializer block out of the Powerdown state, the system drives LVDS_TxPwdn high and sets the
TXPWDN bit. When the Serializer exits Powerdown, its PLL must lock to the LVDS_TxClk before it is ready for
the Initialization state. The system must then allow time for Initialization before data transfer can begin.
NOTE
The associated reference clock must always be active for a change of state on the
receiver powerdowns. That is LVDS_ARefClk for LVDS_APwdn and LVDS_BRefClk for
LVDS_BPwdn must be active to have an effect.
LOOPBACK TEST OPERATION
The DS92UT16 includes two Loopback modes for testing the device functionality and the transmission line
continuity. They are the Line Loopback and the Local Loopback modes.
The Line Loopback connects the serial data input (LVDS_ADin or LVDS_BDin) to the serial data output
(LVDS_ADout and LVDS_BDout). The input signal also routes to the parallel data input of the TCS
DisAssembler. In the Line Loopback mode, the serial input stream goes through deserializer, passes to both the
DisAssembler and the serializer inputs, and then is transmitted out onto the transmission line.
The Local Loopback connects the serial data output from the serializer back to the serial data input of the
deserializer. The connection route includes all the functional blocks of the DS92UT16 except for the LVDS serial
output buffers and LVDS receiver input.
The ALBC register controls the loopbacks with the LNEN, LNSEL, LCLA and LCLB bits.
LOOP TIMING OPERATION
The DS92UT16 includes a Loop Timing mode controlled by the LT bit of the GCS register, see GENERAL
CONTROL AND STATUS—0x03 GCS. On reset the LT bit is clear so the LVDS transmit clock is sourced directly
from the LVDS_TxClk pin. Setting the LT bit will switch the transmit clock to be sourced from the recovered clock
of the active receiver, as defined by the LBA bit of the LKSC register, see LINK STATUS AND CONTROL—0x08
LKSC. The LVDS transmit and TCA blocks will then be driven by this internal clock and not the LVDS_TxClk pin.
Switching to or from Loop Timing mode will cause the transmitted scrambler sequence to change. This will cause
the far end device to loose scrambler lock. However, it may take a number of frames for the far end device to
register the lose of scrambler lock because of the setting of the confidence counter, see DESCRAMBLER
OPERATION. The far end device will then relock to the new scrambler sequence and operation will resume as
normal.
Also, when operating in Loop Timing mode, then a Loss of Lock on the active LVDS receiver, or a switch of
active receiver, will also cause the transmitted scrambler sequence to change. This again will cause the far end
device to loose scrambler lock. The far end device will then relock to the new scrambler sequence and operation
will resume as normal.
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: DS92UT16
Submit Documentation Feedback
33