DS92UT16 Datasheet, PDF (76/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

DS92UT16
OBSOLETE
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
RECEIVE PORT B HEC COUNT—0x6E to 0x70 RBHECC2 to RBHECC0
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Table 65. RBHECC2–RBHECC0
7
6
RBHECC2
0x6E
RBHECC2[7] RBHECC2[6]
RBHECC1
0x6F
RBHECC1[7] RBHECC1[6]
RBHECC0
0x70
RBHECC0[7] RBHECC0[6]
Type: Read only/Clear on Read
5
RBHECC2[5]
RBHECC1[5]
RBHECC0[5]
4
RBHECC2[4]
RBHECC1[4]
RBHECC0[4]
3
RBHECC2[3]
RBHECC1[3]
RBHECC0[3]
2
RBHECC2[2]
RBHECC1[2]
RBHECC0[2]
1
RBHECC2[1]
RBHECC1[1]
RBHECC0[1]
0
RBHECC2[0]
RBHECC1[0]
RBHECC0[0]
Software Lock: No
Reset Value: 0x00
The RBHECC2, RBHECC1 and RBHECC0 registers contain the Port B received errored HEC count.
• RBHECC2–RBHECC0 This register must be read in the order of most significant byte RBHECC2 first and
least significant byte RBHECC0 or the value read will not be valid. This counter will not roll-over from
0xFFFFFF to 0x000000 but will stick at 0xFFFFFF.
RECEIVE PORT B HEC THRESHOLD—0x71 to 0x73 RBHECT2 to RBHECT0
Table 66. RBHECT2–RBHECT0
7
RBHECT2
0x71
RBHECT2[7]
RBHECT1
0x72
RBHECT1[7]
RBHECT0
0x73
RBHECT0[7]
Type: Read/Write
6
RBHECT2[6]
RBHECT1[6]
RBHECT0[6]
5
RBHECT2[5]
RBHECT1[5]
RBHECT0[5]
4
RBHECT2[4]
RBHECT1[4]
RBHECT0[4]
3
RBHECT2[3]
RBHECT1[3]
RBHECT0[3]
2
RBHECT2[2]
RBHECT1[2]
RBHECT0[2]
1
RBHECT2[1]
RBHECT1[1]
RBHECT0[1]
0
RBHECT2[0]
RBHECT1[0]
RBHECT0[0]
Software Lock: No
Reset Value: 0xFF
The RBHECT2, RBHECT1 and RBHECT0 registers contain the Port B received erred HEC threshold. When the
error count RBHECC equals the threshold RBHECT, then the RBXHEC alarm will be set.
These registers should not be set to all zeroes.
• RBHECT2–RBHECT0 Most significant byte RBHECT2 and least significant byte RBHECT0.
76
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