DS92UT16 Datasheet, PDF (32/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

DS92UT16
OBSOLETE
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
www.ti.com
DATA TRANSFER
After initialization, the Serializer is able to transfer data to the Deserializer. The serial data stream includes a start
bit and stop bit appended by the serializer, which frame the sixteen data bits. The start bit is always high and the
stop bit is always low. The start and stop bits also function as clock bits embedded in the serial stream.
The Serializer block accepts 16-bit data from the TCS Assembler block. The internal version of the LVDS_TxClk
signal latches the incoming data. If the LVDS_Synch input or the TXSYNC bit of the LVC register is high for 5
LVDS_TxClk cycles, the Serializer does not latch data from the TCS Assembler block.
The Serializer transmits the data and clock bits (16+2 bits) at 18 times the LVDS_TxClk frequency. For example,
if LVDS_TxClk is 50 MHz, the serial rate is 50 X 18 = 900 Mbps. Since only 16 bits are from input data, the serial
“payload’’ rate is 16 times the LVDS_TxClk frequency. For instance, if LVDS_TxClk = 50 MHz, the payload data
rate is 50 X 16 = 800 Mbps. LVDS_TxClk is provided by the data source and must be in the range of 30 MHz to
52 MHz.
When the Port A Deserializer channel synchronizes to the input from a Serializer, it drives its LVDS_ALock_n pin
low, the LLOSA bit of the ETXRXA register is cleared and valid data is delivered to the TCS DisAssembler. The
process flow is that the Port A Deserializer locks to the embedded clock, uses it to generate multiple internal data
strobes, and then drives the recovered clock on the LVDS_ARxClk pin. The LVDS_ARxClk is synchronous to the
data delivered to the TCS DisAssembler. While the LVDS_ALock_n pin is low, data to the TCS DisAssembler is
valid. Otherwise, the data is invalid and is ignored by the TCS DisAssembler and an interrupt may be raised on
the LLOSA bit being set high.
LVDS_ALock_n and LVDS_ARxClk signals will drive a minimum of three CMOS input gates, a 15 pF total load.
The Port A Deserializer input pins LVDS_ADin are high impedance during Receiver Powerdown (LVDS_APwdn
pin low or bit RAPWDN of the LVC register set high) and power-off (V_CC = 0V).
RESYNCHRONIZATION
Whenever the Port A Deserializer loses lock, it will automatically try to resynchronize. For example, if the
embedded clock edge is not detected two times in succession, the PLL loses lock and the LVDS_ALock_n pin
and the LLOSA bit are driven high. The Port A Deserializer then enters the operating mode where it tries to lock
to a random data stream. It looks for the embedded clock edge, identifies it and then proceeds through the
synchronization process.
The logic state of the LVDS_ALock_n pin indicates whether the data is valid; when it is low, the data is valid. The
system must monitor the LVDS_ALock_n pin and LLOSA bit to determine whether received data is valid. The
DS92UT16 facilitates this by allowing an interrupt to be raised on LLOSA being set. There is a short delay in
response to the PLL losing synchronization to the incoming data stream.
The user can choose to resynchronize to the random data stream or to force fast synchronization by pulsing the
Serializer LVDS_Synch pin or setting the TXSYNC bit. This scheme is left up to the user discretion. One
recommendation is to provide a feedback loop using the LVDS_ALock_n pin itself to control the sync request of
the Serializer, which is the LVDS_Synch pin.
32
Submit Documentation Feedback
Product Folder Links: DS92UT16
Copyright © 2002–2013, Texas Instruments Incorporated