DS92UT16 Datasheet, PDF (58/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

DS92UT16
OBSOLETE
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
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• CEN Coset enable. When set then the optional coset x⁶ + x⁴ + x² + 1 is added to the generated CRC-8 used
for the HEC. When clear the coset is not added to the HEC.
• ECCA ECC active on Port A bit. When set, this indicates to the ECC transmit section that the ETXBR bit (see
ECC TRANSMIT BUFFER AND RECEIVE LVDS ALARMS—0x0A ETXRXA) will be set only when the far end
ECC receiver connected to Port A indicates via the ECC signaling (received ESSA or ESSB signal, as
selected by bit RAESS of register RACTL) over Port A that the message has been received successfully.
When clear the ECC signaling over Port A will be ignored as the ECC Port A receiver is disabled and the
ERABF bit will be held clear. See Embedded Communication Channel Operation.
• ECCB ECC active on Port B bit. When set, this indicates to the ECC transmit section that the ETXBR bit (see
ECC TRANSMIT BUFFER AND RECEIVE LVDS ALARMS—0x0A ETXRXA) will be set only when the far end
ECC receiver connected to Port B indicates via the ECC signaling (received ESSA or ESSB signal, as
selected by bit RBESS of register RBCTL) over Port B that the message has been received successfully.
When clear the ECC signaling over Port B will be ignored as the ECC Port B receiver is disabled and the
ERBBF bit will be held clear. See Embedded Communication Channel Operation.
• ECCB and ECCA Note that when both these bits are clear, then the ECC transmitter and both receivers are
inactive. The ETXBR, ETXSD, ERABF and ERBBF bits will be held clear, the ECC signaling is ignored and
no messages are transmitted or received. See Embedded Communication Channel Operation.
• ECCB and ECCA Note that when both these bits are set, this indicates to the ECC transmit section that the
ETXBR bit will only be set when both far end ECC receivers indicate that the transmitted message has been
received successfully (received ESS signals). See Embedded Communication Channel Operation.
• ABSC A/B Switch completed. When switching active traffic receive port this bit can be polled by the
processor to determine when the switch has been completed successfully. A change of the LBA bit will clear
this bit. The ABSC bit should then be polled by the processor. The ABSC bit is set by the hardware when the
active port switching is completed. This bit relates to the LBA active traffic switching bit and is not related to
the ECC port switching bit ECCA and ECCB. See Switching Receive Ports.
• LBA Local receive port A or B control. When this bit is set, then Receive Port B is Active and Port A is
Standby. When clear, then Port A is Active and Port B is Standby. This bit defines the active traffic port and
does not affect which ECC channel is active as defined by the ECCA and ECCB bits above. See Switching
Receive Ports.
• FTXSCR Force Transmit Scrambler Sequence. When set this forces the transmission of the scrambler
sequence which is used to lock the descrambler.
TRANSMIT LINK LABEL—0x09 TXLL
Table 28. TXLL
7
TXLL[7]
Type: Read/Write
6
TXLL[6]
5
TXLL[5]
4
TXLL[4]
3
TXLL[3]
2
TXLL[2]
1
TXLL[1]
0
TXLL[0]
Software Lock: No
Reset Value: 0x00
The Transmit Link Label register defines the contents of the Link Trace Label byte transmitted in TC6.
• TXLL[7:0] Transmitted Link Trace Label byte contents.
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