DS92UT16 Datasheet, PDF (72/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

DS92UT16
OBSOLETE
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
RECEIVE PORT A FRAME DELINEATION THRESHOLDS—0x41 RAFDT
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Table 56. RAFDT
7
MU[3]
Type: Read/Write
6
MU[2]
5
MU[1]
4
MU[0]
3
2
1
0
SIGMA[3] SIGMA[2] SIGMA[1] SIGMA[0]
Software Lock: Yes
Reset Value: 0x78
The Receive Port A Frame Delineation Thresholds register controls the operation of the Port A frame delineation
state machine. The frame delineation lock status is refiected in the RALFLL bit of the RALA register.
• MU[3:0] When in lock this is the number of consecutive incorrect cell HEC’s required to lose frame
delineation lock.
• SIGMA[3:0] When out of lock this is the number of consecutive correct frame HEC’s required to gain frame
delineation lock.
RECEIVE PORT A DESCRAMBLER LOCK THRESHOLDS—0x42 RADSLKT
Table 57. RADSLKT
7
PSI[3]
Type: Read/Write
6
PSI[2]
5
PSI[1]
4
PSI[0]
3
RHO[3]
2
RHO[2]
1
RHO[1]
0
RHO[0]
Software Lock: Yes
Reset Value: 0x88
The Receive Port A Descrambler Lock Thresholds register controls the operation of the Port A descrambler lock
state machine confidence counter. The descrambler lock status is reflected in the RALDSLL bit of the RALA
register.
• PSI[3:0] When in lock this is the threshold that the descrambler confidence counter must reach to lose
descrambler lock. When in lock the descrambler confidence counter increments on incorrect HEC predictions
and decrements on good HEC predictions.
• RHO[3:0] When out of lock this is the threshold that the descrambler confidence counter must reach to gain
descrambler lock. When out of lock the descrambler confidence counter decrements on incorrect HEC
predictions and increments on good HEC predictions.
72
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