DS92UT16 Datasheet, PDF (39/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

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DS92UT16
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SNOS992E – JANUARY 2002 – REVISED APRIL 2013
Both Receive Port A and Receive Port B maintain Up2Down_ATM loopback counts. The registers that maintain
these counts are the Receive Port A Up2Down Loopback Cell Count register, RAU2DLBC, and the Receive Port
B Up2Down Loopback Cell Count register, RBU2DLBC. See RECEIVE PORT A UP2DOWN LOOPBACK CELL
COUNT—0x3E RAU2DLBC and RECEIVE PORT B UP2DOWN LOOPBACK CELL COUNT—0x7E RBU2DLBC.
Whenever the counter in the Active receiver (as defined by the LBA bit of the LKSC, see LINK STATUS AND
CONTROL—0x08 LKSC) increments, the U2DLBC alarm in the UAA register is set. See UTOPIA AND ATM
ALARMS—0xE1 UAA. Although each counter increments whenever it detect an incoming loopback cell, only
increments to the active receiver’s counter can set the alarm. Note that received loopback cells increment these
counters. So the U2DLBC counter increments on incoming loopback cells.
Alarms in the UAA register will raise an interrupt if the appropriate interrupt enables are set in the UAIE register.
See UTOPIA AND ATM INTERRUPT ENABLES—0xE2 UAIE.
Loopback cells are only counted and looped-back in the appropriate loopback mode. If the loopback mode is not
set then any incoming loopback cells are simply treated as normal traffic cells and passed by the device. In
Up2Down_ATM loopback mode, only cells from the Active receiver will be looped-back.
A loopback cell transmission may be initiated by the DS92UT16 over the LVDS transmit link. The TXLVLB bit in
the ALBC register controls this functionality. Setting the TXLVLB bit causes a single loopback cell to be
transmitted over the LVDS transmit link. When the DS92UT16 finishes transmitting the loopback cell, it
automatically clears the TXLVLB bit. So, the processor, on setting the TXLVLB bit, should poll it to detect that it
clears before trying to set it again to send another loopback cell. The loopback cell transmitted will have a header
of the format defined by the ALBCF3–ALBCF0 registers and an MPhy address as defined by the ALBMP register
Embedded Communication Channel Operation
This section describes the ECC operation. The ECC transmits one 8 byte message per frame over the link under
software control. Flow control ensures that messages are not overwritten at the receive end.
The message to be transmitted is written to the ETXD7–EXTD0 transmit buffer registers and the received
messages are stored in the Port A ERAD7–ERAD0 or Port B ERBD7–ERBD0 receive buffer registers. Software
control is achieved on the transmit side using the ECC Transmit Buffer Ready (ETXBR) interrupt of the ETXRXA
register and the ECC Transmit Send (ETXSD) register.
There are independent receive sections in Port A and Port B and these are controlled using the ECC Receive
Port A Buffer Full (ERABF) interrupt of the Receive Port A Local Alarm (RALA) register, and the ECC Receive
Port B Buffer Full (ERBBF) interrupt of the Receive Port B Local Alarm (RBLA) register respectively. The choice
of receiving ECC messages on Port A or Port B is controlled by the ECCB and ECCA bits of the Link Status and
Control (LKSC) register.
The Remote Alarm and Signaling Byte carries the ECC signaling bits. The transmitted Remote Alarm and
Signaling Byte carries the ESS signal for both of the local ECC receive sections, ESSA and ESSB. At the
receiver a choice must be made as to which ESS bit of the received Remote Alarm and Signaling Byte is valid
for the local ECC transmitter. This is controlled by the RAESS and RBESS bits of the RACTL and RBCTL
registers respectively.
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