DS92UT16 Datasheet, PDF (63/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

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DS92UT16
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SNOS992E – JANUARY 2002 – REVISED APRIL 2013
stored in the FIB traffic queue but transmitted back out over the UTOPIA interface. See ATM CELL
LOOPBACK.
• U2DLB When set, this enables the ATM Up2Down loopback circuit. Any incoming cells from the active LVDS
receive port which match the format of ALBCF3–ALBCF0 registers, masked by the ALFLT3–ALFLT0
registers, are not stored in the MTB traffic queue but transmitted back out over the LVDS transmitter. Note
that although there are two independent receivers, this loopback is designed to operate on live traffic and so
only affects cells from the active receiver as defined by the LBA bit of the LKSC register. See ATM CELL
LOOPBACK.
ATM LOOPBACK MPhy—0x1B ALBMP
Table 38. ALBMP
7
Reserved
Type: Read/Write
6
Reserved
5
Reserved
4
LBMP[4]
3
LBMP[3]
2
LBMP[2]
1
LBMP[1]
0
LBMP[0]
Software Lock: No
Reset Value: 0x00
The ATM Loopback MPhy register defines the MPhy address attached to the ATM loopback cell. Setting the
TXLVLB bit in the ALBC register initiates these loopback cells.
• LBMP[4:0] ATM loopback cell five bit MPhy address.
ATM LOOPBACK CELL FORMAT —0x1C to 0x1F ALBCF3 to ALBCF0
Table 39. ALBCF3–ALBCF0
7
ALBCF3 0x1C
ALBCF3[7]
ALBCF2 0x1D
ALBCF2[7]
ALBCF1 0x1E
ALBCF1[7]
ALBCF0 0x1F
ALBCF0[7]
Type: Read/Write
6
ALBCF3[6]
ALBCF2[6]
ALBCF1[6]
ALBCF0[6]
5
ALBCF3[5]
ALBCF2[5]
ALBCF1[5]
ALBCF0[5]
4
ALBCF3[4]
ALBCF2[4]
ALBCF1[4]
ALBCF0[4]
3
ALBCF3[3]
ALBCF2[3]
ALBCF1[3]
ALBCF0[3]
2
ALBCF3[2]
ALBCF2[2]
ALBCF1[2]
ALBCF0[2]
1
ALBCF3[1]
ALBCF2[1]
ALBCF1[1]
ALBCF0[1]
0
ALBCF3[0]
ALBCF2[0]
ALBCF1[0]
ALBCF0[0]
Software Lock: No
Reset Value: 0x00
The ALBCF3, ALBCF2, ALBCF1 and ALBCF0 registers define the format of the ATM loopback cell header.
• ALBCF3[7:0] Loopback Cell header byte H1 format.
• ALBCF2[7:0] Loopback Cell header byte H2 format.
• ALBCF1[7:0] Loopback Cell header byte H3 format.
• ALBCF0[7:0] Loopback Cell header byte H4 format.
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