DS92UT16 Datasheet, PDF (45/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

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DS92UT16
www.ti.com
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
Microprocessor Interface Operation
The DS92UT16 contains a flexible microprocessor port capable of interfacing to either Intel or Motorola
processors. In addition to an 8-bit address and 8-bit data bus plus the associated bus protocol control signals,
the port includes an open-drain interrupt signal. This signal may be asserted on the detection of various alarms
within the device and any of the potential internal sources of this interrupt may be individually inhibited via an
interrupt mask.
Powering down a Receive Port inhibits access to the associated registers. This feature saves power when a
Receive Port is not in use. It allows re-reading the last value read from a register associated with that Receive
Port and disallows writing to that port’s registers. Receive Port A (RxA) in Power-down mode inhibits access to
registers described in RECEIVE PORT A LINK LABEL—0x20 RALL to RECEIVE PORT A BIT ERROR
COUNT—0x43 to 0x45 RABEC2 to RABEC0. Receive Port B (RxB) in Power-down mode inhibits access to
registers described in RECEIVE PORT B LINK LABEL—0x60 RBLL to RECEIVE PORT B BIT ERROR
COUNT—0x83 to 0x85 RBBEC2 to RBBEC0. The contents of these registers are not lost or altered in Power-
down mode.
Typical processor Read and Write cycles for this device are shown in Figure 19, Figure 20, Figure 21, Figure 22.
The associated timing for each cycle is given in Table 15, Table 16, Table 17, Table 18.
Figure 19. Intel Write Cycle
Table 15. Intel Write
No.
Parameter
1 Address Setup Time before Chip Select Low
2 Chip Select Setup before Write Low
3 Write Pulse Width⁽¹⁾⁽²⁾
4 Data Setup before Write High⁽¹⁾⁽²⁾
5 Data Hold after Write High
6 Chip Select Hold after Write High
7 Address Hold after Write High
8 Write Recovery Time⁽¹⁾⁽³⁾
Min
0
5
6 cycles
5 cycles
5
5
0
1 cycle
Max
Units
ns
ns
ns
ns
ns
(1) “Cycle” must be greater than or equal to the cycle time of the slowest DS92UT16 clock.
(2) When an LVDS receiver loses or gains “lock”, the recovered clock may stay high for up to 2.5 cycles.
If a processor access is in progress to one of the registers in either of the recovered clock domains,
then a READ will return the value of the last READ access, and a WRITE will not change the value of
the target register. To accommodate this possible gap in the clock, 3 cycles has been added to these
timings and they should therefore be regarded as worst case. If access time needs to be increased
and a system is robust enough to accept these possible incorrect accesses then 3 cycles can be
removed from these timings.
(3) A recovery time of 1 cycle is required between successive processor accesses.
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