DS92UT16 Datasheet, PDF (9/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

OBSOLETE
DS92UT16
www.ti.com
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
Transport Container Delineation and Error Monitoring
In the down-bridge direction, the device calculates and inserts the HEC byte using the CRC-8 polynomial x⁸ + x²
+ x + 1 and optional coset x⁶ + x⁴ + x² + 1 defined in I.432.1 [2.]. The HEC byte is calculated over the preceding
7–19 bytes, which make up the link TC header. To aid delineation at the far end, the entire contents of the TC,
excluding the HEC, are scrambled and the HEC is calculated on the scrambled TC header. A scrambler using
the pseudo-random sequence polynomial x³¹ + x²⁸ + 1 defined in I.432.1 [2.] is used.
In the up-bridge direction, the device determines the cell delineation within the received data by locking onto the
HEC byte within the transport container, using the algorithm specified in I.432.1 [2.].
During normal operation in the up-bridge direction, the device monitors the HEC bytes for errors, with an option
to reject cells containing errored HEC’s. A performance metric on the number of errored cells detected is
maintained.
Although the HEC byte normally over-writes the UDF1 byte before cells are passed out over a physical medium,
the DS92UT16 has the option to retain the UDF1 and UDF2 information fields in order to provide a truly
transparent UTOPIA bridge. If it is not necessary to pass the UDF1/2 bytes between the ATM and PHY devices
at either end of the link, then the user has the option to suppress them to improve link efficiency.
Furthermore, in order to easily share-out the F Channel bandwidth between flow control and various OAM
functions, the DS92UT16 uses a frame structure as shown in F Channel Byte Usage Within the Frame. A frame
contains 56 transport containers with ATM cells. The start of frame is indicated by the HEC byte of TC0, which
has had the coset x⁶ + x⁴ + x² + 1 added to it. This differentiates the start of frame HEC from the normal cell
HEC’s.
Flow Control
The flow control mechanism within the DS92UT16 enables applying back-pressure to the source of the ATM
cells in both directions. The flow control works independently per queue for all 31 queues. It uses a simple
‘halt/send’ command per PHY Port. At the destination buffer, the fill level of each Port queue is examined against
a programmed threshold. Should the threshold be reached, a halt command is returned to the source, which
prevents any more cells being sent to that Port until a ‘send’ command is subsequently received. Only the Port in
question is affected, so this is a non-blocking protocol over the normal 31 Ports. However, the 8 sub-ports within
a Port do not have individual flow control. This means a sub-port can block other sub-ports within that Port.
Since a regular flow control opportunity is provided via the F1/F2 bytes of the F Channel, only a small amount of
headroom need be reserved to allow for latency in this protocol. Furthermore, should a number of PHY ports
approach their limit simultaneously and/or the overall buffer approach a defined global threshold, a global halt
may be issued, temporarily blocking all traffic.
The global halt/send command also allows the user to safely maximize the use of the shared buffer by over-
assigning the memory among the Ports.
The flow control command is illustrated in Table 3. Each port is assigned a control bit in specified F-bytes within
the frame structure, as shown in F Channel Byte Usage Within the Frame. Within the F byte logic, 1 represents a
‘halt’ command to that port and logic 0 represents a ‘send’ command. A global halt is indicated by all ports
containing a halt command. The msb of Flow Control 3 byte is reserved.
Table 3. Flow Control Coding Within the F Bytes
Flow
Control 3
Flow
Control 2
Flow
Control 1
Flow
Control 0
Res
Ports 30–24 Ports 23–16 Ports 15–8 Ports 7–0
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: DS92UT16
Submit Documentation Feedback
9