DS92UT16 Datasheet, PDF (47/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

www.ti.com
OBSOLETE
DS92UT16
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
Figure 21. Motorola Write Cycle
Table 17. Motorola Write
No.
Parameter
1 Address Setup Time before Chip Select Low
2 Chip Select Setup before Data Strobe Low
3 Read/Write Setup before Data Strobe Low
4 Data Strobe Pulse Width⁽¹⁾⁽²⁾
5 Data Setup before Data Strobe High⁽¹⁾⁽²⁾
6 Data Hold after Data Strobe High
7 Read/Write Hold after Data Strobe High
8 Chip Select Hold after Data Strobe High
9 Address Hold after Data Strobe High
10 Data Strobe Recovery Time⁽¹⁾⁽³⁾
Min
0
0
5
6 cycles
5 cycles
5
5
5
0
1 cycle
Max
Units
ns
ns
ns
ns
ns
ns
ns
(1) “Cycle” must be greater than or equal to the cycle time of the slowest DS92UT16 clock.
(2) When an LVDS receiver loses or gains “lock”, the recovered clock may stay high for up to 2.5 cycles.
If a processor access is in progress to one of the registers in either of the recovered clock domains,
then a READ will return the value of the last READ access, and a WRITE will not change the value of
the target register. To accommodate this possible gap in the clock, 3 cycles has been added to these
timings and they should therefore be regarded as worst case. If access time needs to be increased
and a system is robust enough to accept these possible incorrect accesses then 3 cycles can be
removed from these timings.
(3) A recovery time of 1 cycle is required between successive processor accesses.
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: DS92UT16
Submit Documentation Feedback
47