DS92UT16 Datasheet, PDF (81/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

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DS92UT16
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SNOS992E – JANUARY 2002 – REVISED APRIL 2013
RECEIVE PORT B DESCRAMBLER LOCK THRESHOLDS—0x82 RBDSLKT
Table 76. RBDSLKT
7
PSI[3]
Type: Read/Write
6
PSI[2]
5
PSI[1]
4
PSI[0]
3
RHO[3]
2
RHO[2]
1
RHO[1]
0
RHO[0]
Software Lock: Yes
Reset Value: 0x88
The Receive Port B Descrambler Lock Thresholds register controls the operation of the Port B descrambler lock
state machine confidence counter. The descrambler lock status is refiected in the RBLDSLL bit of the RBLA
register.
• PSI[3:0] When in lock this is the threshold that the descrambler confidence counter must reach to lose
descrambler lock. When in lock the descrambler confidence counter increments on incorrect HEC predictions
and decrements on good HEC predictions.
• RHO[3:0] When out of lock this is the threshold that the descrambler confidence counter must reach to gain
descrambler lock. When out of lock the descrambler confidence counter decrements on incorrect HEC
predictions and increments on good HEC predictions.
RECEIVE PORT B BIT ERROR COUNT—0x83 to 0x85 RBBEC2 to RBBEC0
Table 77. RBBEC2–RBBEC0
7
6
RBBEC2
0x83
RBBEC2[7] RBBEC2[6]
RBBEC1
0x84
RBBEC1[7] RBBEC1[6]
RBBEC0
0x85
RBBEC0[7] RBBEC0[6]
Type: Read only/Clear on Read
5
RBBEC2[5]
RBBEC1[5]
RBBEC0[5]
4
RBBEC2[4]
RBBEC1[4]
RBBEC0[4]
3
RBBEC2[3]
RBBEC1[3]
RBBEC0[3]
2
RBBEC2[2]
RBBEC1[2]
RBBEC0[2]
1
RBBEC2[1]
RBBEC1[1]
RBBEC0[1]
0
RBBEC2[0]
RBBEC1[0]
RBBEC0[0]
Software Lock: No
Reset Value: 0x00
The RBBEC2, RBBEC1 and RBBEC0 registers contain the Port B received bit error count whenever the RBBEC
bit of the RBCTL register is set. If the RBBEC bit of the RBCTL register is clear, these registers are cleared.
• RBBEC2–RBBEC0 This register must be read in the order of most significant byte RBBEC2 first and least
significant byte RBBEC0 last, or the value read will not be valid. This counter will not roll-over from 0xFFFFFF
to 0x000000 but will stick at 0xFFFFFF.
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