DS92UT16 Datasheet, PDF (16/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

DS92UT16
OBSOLETE
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
Signal Description
Package ball assignment in Package
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PIN DESCRIPTION
Signal Name
Description
Width
UTOPIA INTERFACE
U_TxData [15:0]
Transmit toward the PHY Layer data bus.
16
U_TxParity
Transmit data bus parity bit. (odd parity)
1
U_TxCLAV [7:1]
Transmit cell available - Extended.
7
U_TxCLAV [0]
Transmit cell available - Normal/Extended.
1
U_TxENB [7:1]
Enable Data transfers - Extended.
7
U_TxENB [0]
Enable Data transfers - Normal/Extended.
1
U_TxSOC
Transmit Start Of Cell.
1
U_TxAddr [4:0]
Address of MPHY device being selected.
5
U_RxData [15:0]
Receive from the PHY Layer data bus.
16
U_RxParity
Receive data bus parity bit. (odd parity)
1
U_RxCLAV [7:1]
Receive cell available - Extended.
7
U_RxCLAV [0]
Receive cell available - Normal/Extended.
1
U_RxENB [7:1]
Enable Data transfers - Extended.
7
U_RxENB [0]
Enable Data transfers - Normal/Extended.
1
U_RxSOC
Receive Start Of Cell.
1
U_RxAddr [4:0]
Address of MPHY device being selected.
5
U_UDBClk
UTOPIA Down Bridge - Input transfer clock.
1
U_UUBClk
UTOPIA Up Bridge - Output transfer clock.
1
LVDS INTERFACE
LVDS_ADout[+,−]
A Serial data differential outputs.
2
LVDS_BDout[+,−]
B Serial data differential outputs.
2
LVDS_ADenb
Serial transmit data A output enable.
1
LVDS_BDenb
Serial transmit data B output enable.
1
LVDS_Synch
External control to transmit SYNCH patterns on serial
1
interface.
LVDS_TxClk
Transmit clock.
1
LVDS_TxPwdn
Transmit section power down
1
LVDS_ADin[+,−]
PortA Serial data differential inputs.
2
LVDS_ALock_n
PortA Clock recovery lock status
1
LVDS_ARxClk
PortA Recovered clock.
1
LVDS_ARefClk
PortA Reference clock for receive PLLs.
1
LVDS_APwdn
PortA Power Down.
1
LVDS_BDin[+,−]
PortB Serial data differential inputs.
2
LVDS_Block_n
PortB Clock recovery lock status.
1
LVDS_BRxClk
PortB Recovered clock.
1
LVDS_BRefClk
PortB Reference clock for receive PLLs.
1
LVDS_BPwdn
PortB Power Down.
1
Signal Type
Polarity
BiDir ⁽¹⁾
BiDir ⁽¹⁾
Input ⁽²⁾
BiDir ⁽³⁾
Output ⁽²⁾
BiDir ⁽¹⁾
BiDir ⁽¹⁾
BiDir ⁽¹⁾
BiDir ⁽³⁾
BiDir ⁽³⁾
Input ⁽²⁾
BiDir ⁽³⁾
Output ⁽²⁾
BiDir ⁽¹⁾
BiDir ⁽³⁾
BiDir ⁽¹⁾
Input ⁽⁴⁾
Input ⁽⁵⁾
Active High
Active High
Active Low
Active Low
Active High
Active High
Active High
Active Low
Active Low
Active High
Output
Output
Input
Input
Input
Input
Input
Input
Output
Output
Input
Input
Input
Output
Output
Input
Input
Active High
Active High
Active High
Active Low
Active Low
Active Low
Internal
Bias
Pull Down
Pull Down
Pull Down
Pull Down
Pull Up
Pull Up
Pull Down
Pull Up
Pull Up
Pull Up
(1) These pins are Outputs in ATM Layer mode and Inputs PHY Layer mode.
(2) These pins are only used in PHY layer mode, Extended 248 PHY mode. In Normal 31 PHY mode or ATM layer mode, they must be
unconnected.
(3) These pins are Inputs in ATM Layer mode and Outputs PHY Layer mode
(4) In PHY layer mode this is the Utopia TxClk and in ATM layer mode this is the Utopia RxClk.
(5) In PHY layer mode this is the Utopia RxClk and in ATM layer mode this is the Utopia TxClk.
16
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