DS92UT16 Datasheet, PDF (31/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

OBSOLETE
DS92UT16
www.ti.com
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
INITIALIZATION
Before the DS92UT16 sends or receives data, it must initialize the links to and from another DS92UT16.
Initialization refers to synchronizing the Serializer’s and the Deserializer’s PLL’s to local clocks. The local clocks
must be the same frequency or within a specified range if from different sources. After the Serializers
synchronize to the local clocks, the Deserializers synchronize to the Serializers as the second and final
initialization step.
Step 1: After applying V_CC and GND to the Serializer and Deserializer, the LVDS transmit outputs are held in
TRI-STATE and the on-chip power-sequencing circuitry disables the internal circuits. When V_CC reaches V_CCOK
(2.2V) in each device, the PLL in the serializer and deserializer begins locking to the local clock. In the Serializer,
the local clock is the LVDS_TxClk, while in the Port A Deserializer it is the reference clock, LVDS_ARefClk. A
local on-board oscillator or other source provides the specified clock input to the LVDS_TxClk and
LVDS_ARefClk pins.
The Serializer outputs remain in TRI-STATE until the PLL locks to the LVDS_TxClk. After locking to
LVDS_TxClk, the Serializer block is now ready to send data or synchronization patterns. If the LVDS_Synch pin
is high, or the TXSYNC bit of the LVC register is set (see LVDS CONTROL—0x04 LVC), then the Serializer
block generates and sends the synchronization patterns (sync-pattern).
The internal Port A Deserializer data outputs remain invalid while the PLL locks to the reference clock.
When the Port A Deserializers PLL locks to incoming data or sync-pattern on the LVDS_ADin pins, it will clear
the corresponding Local Loss Of Signal bit, LLOSA, in the ETXRXA register (see ECC TRANSMIT BUFFER
AND RECEIVE LVDS ALARMS—0x0A ETXRXA) and the lock pin LVDS_ALock_n will go low.
Step 2: The Deserializer PLL must synchronize to the Serializer to complete the initialization. The Serializer that
is generating the stream to the Deserializer must send random (non-repetitive) data patterns or sync-patterns
during this step of the Initialization State. The Deserializer will lock onto sync-patterns within a specified amount
of time. The lock to random data depends on the data patterns and, therefore, the lock time is unspecified.
In order to lock to the incoming LVDS data stream, the Deserializer identifies the rising clock edge in a sync-
pattern and will synchronize to the embedded clock in less than 5 µs. If the Deserializer is locking to a random
data stream from the Serializer, then it performs a series of operations to identify the rising clock edge and locks
to it. Because this locking procedure depends on the data pattern, it is not possible to specify how long it will
take. At the point where the Port A Deserializer’s PLL locks to the embedded clock, the LVDS_ALock_n pin goes
low, the LLOSA bit of the ETXRXA register may be cleared and valid data is presented to the TCS DisAssembler
block. Note that the LVDS_ALock_n signal is synchronous to valid data being presented to the TCS
DisAssembler.
The user’s application determines whether sync-patterns or lock to random data is the preferred method for
synchronization. If sync-patterns are preferred, the associated Port A deserializer’s LVDS_ALock_n pin is a
convenient way to provide control of the LVDS_Synch pin, possibly via the RARLOSA (Receive Port A, Remote
Loss Of Signal) bit of the RARA register, see RECEIVE PORT A REMOTE STATUS AND ALARMS—0x3C
RARA.
Copyright © 2002–2013, Texas Instruments Incorporated
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