DS92UT16 Datasheet, PDF (60/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

DS92UT16
OBSOLETE
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
ECC TRANSMIT BUFFER SEND—0x0C ETXSD
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Table 31. ETXSD
7
Reserved
Type: Read/Write
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
ETXSD
Software Lock: No
Reset Value: 0x00
The ETXSD register bit controls the transmission of an ECC message.
• ETXSD The setting of the ETXSD bit initiates the transmission of the ECC message in the ETXD0–ETXD7
data registers, but only if the ETXBR is also set. Once transmission of a message has been initiated in this
way, it will proceed until the far end ECC receiver indicates, via the ECC signaling, that the message has
been received successfully. The ETXSD bit will be cleared and the ETXBR register bit is set automatically
when the far end ECC receiver indicates that the message has been received successfully. To re-send the
same message simply set the ETXSD bit again.
• See Embedded Communication Channel Operation for a complete description of the Embedded
Communication Channel operation.
• The processor can halt transmission of a message by clearing the ETXSD bit which sets the ETXBR bit to
enable a new message to be constructed in the ETXD7–ETXD0 registers.
ECC TRANSMIT BUFFER—0x0D to 0x14 ETXD7 to ETXD0
Table 32. ETXD7–ETXD0
7
ETXD7 0x0D ETXD7[7]
ETXD6 0x0E ETXD6[7]
ETXD5 0x0F ETXD5[7]
ETXD4 0x10 ETXD4[7]
ETXD3 0x11 ETXD3[7]
ETXD2 0x12 ETXD2[7]
ETXD1 0x13 ETXD1[7]
ETXD0 0x14 ETXD0[7]
Type: Read/Write
6
ETXD7[6]
ETXD6[6]
ETXD5[6]
ETXD4[6]
ETXD3[6]
ETXD2[6]
ETXD1[6]
ETXD0[6]
5
ETXD7[5]
ETXD6[5]
ETXD5[5]
ETXD4[5]
ETXD3[5]
ETXD2[5]
ETXD1[5]
ETXD0[5]
4
ETXD7[4]
ETXD6[4]
ETXD5[4]
ETXD4[4]
ETXD3[4]
ETXD2[4]
ETXD1[4]
ETXD0[4]
3
ETXD7[3]
ETXD6[3]
ETXD5[3]
ETXD4[3]
ETXD3[3]
ETXD2[3]
ETXD1[3]
ETXD0[3]
2
ETXD7[2]
ETXD6[2]
ETXD5[2]
ETXD4[2]
ETXD3[2]
ETXD2[2]
ETXD1[2]
ETXD0[2]
1
ETXD7[1]
ETXD6[1]
ETXD5[1]
ETXD4[1]
ETXD3[1]
ETXD2[1]
ETXD1[1]
ETXD0[1]
0
ETXD7[0]
ETXD6[0]
ETXD5[0]
ETXD4[0]
ETXD3[0]
ETXD2[0]
ETXD1[0]
ETXD0[0]
Software Lock: No
Reset Value: 0x00
The ETXD7, ETXD6, ETXD5, ETXD4, ETXD3, ETXD2, ETXD1 and ETXD0 registers contain the ECC message
to be transmitted.
• ETXD7–ETXD0 When the ETXBR bit is set, then these registers have full read/write access to allow flexible
assembly of the ECC message before initiating transmission by setting the ETXSD bit. When the ETXBR is
clear during message transmission, these registers are read only so that the message being transmitted
cannot be overwritten and corrupted.
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