DS92UT16 Datasheet, PDF (65/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

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RECEIVE PORT A LOCAL ALARMS —0x22 RALA
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
Table 42. RALA
7
6
5
Reserved RALLC
RALLM
Type: Bits[6:1] Read only/Clear on Read
Bit[0] Read/Write
4
RALCS
3
2
RALDSLL RALTCLL
1
RALFF
0
ERABF
Software Lock: No
Reset Value: 0x00
The Receive Port A Local Alarms register contains information on the status of the Port A disassembler. When
set RALLC, RALLM, RALDSLL, RALTCLL and RALFLL will raise an interrupt if the corresponding interrupt
enable bits are set. Also a change in value on RALDSLL, RALTCLL or RALFLL will set the RALCS bit which will
raise an interrupt if the corresponding interrupt enable bit is set.
• RALLC Receive Port A, Local Link Label Change of Status. Set = Change in RALL register value.
• RALLM Receive Port A, Local Link Label Mismatch. Set = Received link label RALL different than expected
link label RAELL.
• RALCS Receive Port A, Local Change of Status. Set = change in value of RALDSLL, RALTCLL or RALFLL
bits
• RALDSLL Receive Port A, Local Descrambler Loss of Lock. Set = Out of Lock and Clear = Lock.
• RALLTCLL Receive Port A, Local Transport Container Delineation Loss of Lock. Set = Out of Lock and Clear
= Lock.
• RALFLL Receive Port A, Local Frame Delineation Loss of Lock. Set = Out of Lock and Clear = Lock.
The ERABF register bit indicates that the ECC receive section for Port A has successfully received a full ECC
message consisting of the 8 data bytes contained in registers ERAD7–ERAD0, and the message can now be
read by the processor.
On reset, the ERABF will be clear indicating no valid message has been received. When a valid message is
received and stored in the ERAD7–ERAD0 data registers, the ERABF bit will be set and will raise an interrupt if
the corresponding interrupt enable bit is set. Therefore, the processor can detect a received message on the
interrupt or by polling the ERABF bit. When the processor has finished reading the message from the
ERAD7–ERAD0 data registers and is ready to receive a new message it simply clears the ERABF bit. When a
full message has been successfully received this is communicated to the far-end device via the ECC signaling.
• ERABF The ERABF bit, when set, indicates that ERAD7–ERAD0 data registers contain a full valid received
message. The data in the ERAD7–ERAD0 data registers cannot be overwritten with a new received message
while ERABF is set. When ERABF is cleared this allows the ERAD7–ERAD0 data registers to be overwritten
with a new received message.
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