DS92UT16 Datasheet, PDF (25/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

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DS92UT16
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SNOS992E – JANUARY 2002 – REVISED APRIL 2013
MULTIPLE BRIDGE MTB CONFIGURATION
When UTOPIA-LVDS bridges are used in parallel as in Figure 5 the PHY mode DS92UT16s will forward all cells
on the UTOPIA TxData bus across the LVDS bridge. Cells that are not addressed for PHYs on a bridge will
accumulate in the MTBs of the ATM mode DS92UT16s. If too many cells accumulate the MTB will become full
and traffic will be stopped over that bridge. To prevent filling the MTBs PHY port addresses must be distributed
evenly across all bridges in the system. Additionally, the MTB queue threshold of any ports not in the Connected
Ports List should be set to 0 in order to limit the number of cells that can accumulate.
Table 12 lists the minimum number of ports that must be assigned to each bridge for the total number of ports in
the system.
Table 12. Minimum Ports per
Bridge in a Mult-Bridge
System
Total Ports Used
31
30
29
28
27
26
25
24
23
22
Minimum
Number of
Ports per
Bridge
10
9
8
7
6
5
4
3
2
1
Configuration and Traffic Inhibit Operation
Modifying some device configuration settings should not be carried out while traffic is flowing. A mechanism to
inhibit traffic is provided, which should be used when changing any of the settings contained in the PDUCFG,
UCFG, USPAL or USPAM registers.
The Traffic Inhibit mechanism causes traffic to stop. The UTOPIA interface will stop transmitting and receiving
cells, the LVDS transmit section will transmit Idle cells, and the incoming cells on the active LVDS receive port
will be discarded. It is controlled by the Configuration Traffic Inhibit (CTI) and Traffic Inhibit Status (TIS) bits of
the General Control and Status (GCS) register, see GENERAL CONTROL AND STATUS—0x03 GCS.
The processor should set the CTI bit before changing any of the PDUCFG, UCFG, USPAL or USPAM register
settings. This will initiate the Traffic Inhibit mechanism. The TIS bit should then be polled. When the TIS bit is set,
then traffic is inhibited.
The MTB and FIB queues MUST be flushed at this stage. Use the FIBFL and MTBFL bits of the QFL register
described in QUEUE FLUSH—0xD8 QFL to accomplish the queue flushing. Set these bits to flush the queues
and then poll these bits to determine when flushed. The queue flushing is complete when these bits are clear.
The device can now be reconfigured safely. When configuration is completed, then the CTI bit can be cleared by
the processor and normal operation resumed.
NOTE
The CTI bit is set on either power up or software reset (see GENERAL CONTROL AND
STATUS—0x03 GCS) and therefore the Traffic Inhibit mechanism is active. When
initialization of the device registers is completed by the processor the CTI bit should be
cleared.
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