DS92UT16 Datasheet, PDF (29/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

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DS92UT16
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SNOS992E – JANUARY 2002 – REVISED APRIL 2013
DESCRAMBLER OPERATION
Once TC delineation has been obtained, the Descrambler synchronization can begin.
After reset, the Descrambler expects the far-end transmitting device to send it’s Scrambler sequence embedded
in Idle cells so that the Descrambler can synchronize (lock) to it. This scrambler-sequence transfer is achieved by
means of the Remote Descrambler Loss of Lock bit (RDSLL) in the Remote Alarm and Signaling byte (see
Remote Alarm and Signaling Byte). This received bit is stored as the RARDSLL bit of the RARA register for Port
A (see RECEIVE PORT A REMOTE STATUS AND ALARMS—0x3C RARA) and the RBRDSLL bit of the RBRA
register for Port B (see RECEIVE PORT B REMOTE STATUS AND ALARMS—0x7C RBRA).
The lock status of the Descrambler is transmitted to the far-end device as the RDSLL bit. If the Descrambler is
out of lock, then the transmitted RDSLL = 1. At the far end device, this is stored as RARDSLL or RBRDSLL,
depending on which port it is connected to. When this bit is set for the active receive port, it causes the TCS
Assembler to transmit the Scrambler sequence embedded in Idle cells. The Descrambler loads this sequence
and attempts to lock to it. Once the Descrambler locks to this sequence, it clears the RDSLL bit transmitted to
the far-end device, which causes the far-end device to stop sending the Scrambler sequence embedded in Idle
cells and to begin sending real traffic cells.
The Descrambler synchronization state diagram is shown in Figure 14.
Figure 14. State Diagram for Descrambler Synchronization
D_HUNT—On reset, the Descrambler synchronization state machine starts in the D_HUNT state and the
Descrambler is not in Lock. When TC delineation has been achieved, the transmitted Scrambler sequence from
the far-end device is loaded into the Descrambler. The state machine enters the D_PRESYNC state.
D_PRESYNC—The received scrambler sequences and predicted sequences are compared for each TC. For
each correct prediction, a confidence counter increments, and for each incorrect prediction, the confidence
counter is decremented. When the confidence counter reaches RHO, then the state machine moves to the
D_SYNCH state and the system is said to have achieved scrambler Lock. If the confidence counter reaches zero
then the state machine moves back to the HUNT state.
D_SYNC—The comparison of received scrambler sequences and predicted sequences is repeated for each
Frame. For each correct prediction, a confidence counter is decremented, and for each incorrect prediction, the
confidence counter is incremented. The confidence counter has a lower limit of zero. If the confidence counter
reaches PSI, then the state machine moves back to the D_HUNT state and the Descrambler is out of Lock.
The state machine will also return directly to D_HUNT if TC delineation is lost.
The values of PSI and RHO are programmable independently for Port A and Port B. They are contained in the
RADSLKT and RBDSLKT registers (see RECEIVE PORT A DESCRAMBLER LOCK THRESHOLDS—0x42
RADSLKT and RECEIVE PORT B DESCRAMBLER LOCK THRESHOLDS—0x82 RBDSLKT). On reset PSI = 8
and RHO = 8.
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