DS92UT16 Datasheet, PDF (61/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

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DS92UT16
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GENERAL PURPOSE INPUT OUTPUT—0x15 GPIO
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
Table 33. GPIO
7
6
5
4
3
2
1
0
DDR[3]
DDR[2]
DDR[1]
DDR[0]
IO[3]
IO[2]
IO[1]
IO[0]
Type: Bits [7:4] Read/Write
Bits[3:0] are Read Only when GPIO[3:0] are defined as Inputs, and Read/Write when GPIO[3:0] are
defined as Outputs.
Software Lock: No
Reset Value: 0xF0
The General Purpose Input/Output register controls the four general purpose input/output pins GPIO[3:0].
• DDR[3:0] The Data Direction bits DDR[3:0] define the function of the GPIO[3:0] pins. When a DDR bit is set
the corresponding GPIO pin is an input and when the DDR bit is clear the corresponding GPIO pin is an
output.
• IO[3:0] The IO bits reflect the value of the GPIO pins. When defined as an output by the DDR bit, then the IO
bit value is driven out on the corresponding GPIO pin. When defined as an input by the DDR bit, then the IO
bit value captures the incoming value on the corresponding GPIO pin.
TEST ERROR CONTROL—0x16 TERRCTL
Table 34. TERRCTL
7
EBRST[3]
Type: Read/Write
6
EBRST[2]
5
EBRST[1]
4
EBRST[0]
3
ERFHEC
2
ERCHEC
1
ERBIP
0
TXPRBS
Software Lock: Yes
Reset Value: 0x00
The Test Error Control register is used to control the transmission of a PRBS pattern for Bit Error Rate testing, or
to introduce HEC and BIP errors so that the Cell Delineation, Frame Delineation, Descrambler Lock and
performance monitoring functions can be tested. This is a test register and should not be used on live traffic. The
exact nature of the errored HEC and BIP bytes is determined by the ERRBIP1, ERRBIP0 and ERRHEC
registers.
• EBRST[3:0] The Error Burst bits EBRST[3:0] define the number of consecutive erred HEC’s and/or BIP’s to
be generated and transmitted.
• ERFHEC The Error Frame HEC bit, when set, will cause EBRST consecutive Frame HEC’s to be erred.
When this has been completed the hardware will clear this bit.
• ERCHEC The Error Cell HEC bit, when set, will cause EBRST consecutive Cell HEC’s to be erred. When this
has been completed the hardware will clear this bit.
• ERBIP The Error BIP bit, when set, will cause EBRST consecutive BIP’s to be erred. When this has been
completed the hardware will clear this bit.
• TXPRBS Transmit PRBS pattern. When set, the transmit section sends the raw scrambler pseudo-random
sequence (polynomial x³¹ + x²⁸ + 1). No data is transmitted. The TCS Assembler will be paused and no cells
will be read from the FIB queue. The far end receiver can lock to this PRBS pattern to count bit errors if the
RABEC/RBBEC bit is set in the RACTL/RBCTL register. This is not a live traffic test.
Copyright © 2002–2013, Texas Instruments Incorporated
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