DS92UT16 Datasheet, PDF (68/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

DS92UT16
OBSOLETE
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
RECEIVE PORT A HEC THRESHOLD—0x31 to 0x33 RAHECT2 to RAHECT0
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Table 47. RAHECT2–RAHECT0
7
RAHECT2
0x31
RAHECT2[7]
RAHECT1
0x32
RAHECT1[7]
RAHECT0
0x33
RAHECT0[7]
Type: Read/Write
6
RAHECT2[6]
RAHECT1[6]
RAHECT0[6]
5
RAHECT2[5]
RAHECT1[5]
RAHECT0[5]
4
RAHECT2[4]
RAHECT1[4]
RAHECT0[4]
3
RAHECT2[3]
RAHECT1[3]
RAHECT0[3]
2
RAHECT2[2]
RAHECT1[2]
RAHECT0[2]
1
RAHECT2[1]
RAHECT1[1]
RAHECT0[1]
0
RAHECT2[0]
RAHECT1[0]
RAHECT0[0]
Software Lock: No
Reset Value: 0xFF
The RAHECT2, RAHECT1 and RAHECT0 registers contain the Port A received erred HEC threshold. When the
error count RAHECC equals the threshold RAHECT then the RAXHEC alarm will be set.
These registers should not be set to all zeroes.
• RAHECT2–RAHECT0 Most significant byte RAHECT2 and least significant byte RAHECT0.
RECEIVE PORT A BIP COUNT—0x34 to 0x36 RABIPC2 to RABIPC0
Table 48. RABIPC2–RABIPC0
7
6
RABIPC2
0x34
RABIPC2[7] RABIPC2[6]
RABIPC1
0x35
RABIPC1[7] RABIPC1[6]
RABIPC0
0x36
RABIPC0[7] RABIPC0[6]
Type: Read only/Clear on Read
5
RABIPC2[5]
RABIPC1[5]
RABIPC0[5]
4
RABIPC2[4]
RABIPC1[4]
RABIPC0[4]
3
RABIPC2[3]
RABIPC1[3]
RABIPC0[3]
2
RABIPC2[2]
RABIPC1[2]
RABIPC0[2]
1
RABIPC2[1]
RABIPC1[1]
RABIPC0[1]
0
RABIPC2[0]
RABIPC1[0]
RABIPC0[0]
Software Lock: No
Reset Value: 0x00
The RABIPC2, RABIPC1 and RABIPC0 registers contain the Port A received errored BIP count.
• RABIPC2–RABIPC0 This register must be read in the order of most significant byte RABIPC2 first and least
significant byte RABIPC0 last or the value read will not be valid. This counter will not roll-over from 0xFFFFFF
to 0x000000 but will stick at 0xFFFFFF.
68
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