DS92UT16 Datasheet, PDF (88/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

DS92UT16
OBSOLETE
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
ATM DOWN2UP LOOPBACK CELL COUNT—0xE0 D2ULBCC
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Table 90. D2ULBCC
7
6
D2ULBCC D2ULBCC
[7]
[6]
Type: Read only/Clear on Read
5
D2ULBCC
[5]
4
D2ULBCC
[4]
3
D2ULBCC
[3]
2
D2ULBCC
[2]
1
D2ULBCC
[1]
0
D2ULBCC
[0]
Software Lock: No
Reset Value: 0x00
The ATM Down2Up Loopback Cell Count register counts the number of outgoing loopback cells detected on the
UTOPIA interface when Down2Up loopback is enabled with the D2ULB bit of the ALBC register, see ATM AND
LVDS LOOPBACK CONTROL—0x1A ALBC. Note that this counter is only incremented when a loopback cell is
read out of the device.
• D2ULBCC[7:0] Down2Up Loopback Cell Count value. This register will not roll-over from 0x00 to 0xFF but
will stick at 0xFF.
UTOPIA AND ATM ALARMS—0xE1 UAA
Table 91. UAA
7
6
PDULA
CTFRA
Type: Read only/Clear on Read
5
D2ULBC
4
U2DLBC
3
UPRTY
2
1
0
FIBOVA MTBSOVA MTBHOVA
Software Lock: No
Reset Value: 0x00
The UTOPIA and ATM Alarms register monitors the UTOPIA interface, loopbacks and queue overflows. When
set these bits will raise an interrupt if the corresponding interrupt enables are set.
• PDULA PDU Length Alarm bit. Set = PDU length as defined by the PDUCFG register is greater than the
maximum PDU cell length of 64 bytes. Clear = PDU length is less than or equal to maximum of 64 bytes.
• CTFRA Cell Transfer Alarm bit. This alarm is only valid when the device is configured as a PHY layer by
setting the UMODE bit of the UCFG register. It indicates that the controlling ATM layer device has caused an
incorrect cell transfer to or from the DS92UT16. An incorrect cell transfer can only occur when a suspended
cell transfer is restarted with an different MPhy address than initially selected. Set = Incorrect cell transfer has
occurred on the UTOPIA transmit or receive interface.
• D2ULBC Set = D2ULBCC count register has changed value.
• U2DLBC Set = RAU2DLBC or RBU2DLBC count registers have changed value.
• UPRTY Set = A parity error has occurred on an incoming ATM cell byte.
• FIBOV Set = FIB queue attempted to overflow (Equivalent functionality as the MTBQOV3–0 register bits).
• MTBSOV MTB Soft Overflow Alarm bit. Set = One or more of the bits in the MTBQOV3–MTBQOV0 registers
are set. Clear = The MTBQOV3–MTBQOV0 registers are clear.
• MTBHOV MTB Hard Overflow Alarm bit. Set = MTB queue has attempted to overflow. This is a hard overflow
as the overall MTB has attempted to fill beyond it’s hard limit of 159 cells.
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