DS92UT16 Datasheet, PDF (86/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

DS92UT16
OBSOLETE
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
MTB QUEUE FLUSH—0xD0 to 0xD3 MTBQF3 to MTBQF0
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Table 86. MTBQF3–MTBQF0
7
MTBQF3
0xD0
Reserved
MTBQF2
0xD1
MTBQF2[7]
MTBQF1
0xD2
MTBQF1[7]
MTBQF0
0xD3
MTBQF0[7]
Type: Read/Write
6
MTBQF3[6]
MTBQF2[6]
MTBQF1[6]
MTBQF0[6]
5
MTBQF3[5]
MTBQF2[5]
MTBQF1[5]
MTBQF0[5]
4
MTBQF3[4]
MTBQF2[4]
MTBQF1[4]
MTBQF0[4]
3
MTBQF3[3]
MTBQF2[3]
MTBQF1[3]
MTBQF0[3]
2
MTBQF3[2]
MTBQF2[2]
MTBQF1[2]
MTBQF0[2]
1
MTBQF3[1]
MTBQF2[1]
MTBQF1[1]
MTBQF0[1]
0
MTBQF3[0]
MTBQF2[0]
MTBQF1[0]
MTBQF0[0]
Software Lock: Yes
Reset Value: 0x00
The MTBQF3, MTBQF2, MTBQF1 and MTBQF0 registers allow each of the queues to be flushed. Flushing a
queue removes all PDU cells from the queue. The processor sets the appropriate bit in the MTBQF register to
flush a queue. When this has been completed, the hardware will clear the bit. So after setting a bit to flush a
queue, the processor should poll the MTBQF register to determine when the flushing has been completed.
• MTBQF3–MTBQF0 MTBQF3[6] corresponds to queue 31 and MTBQF0[0] corresponds to queue 0. When a
bit is set, then a flush of the corresponding queue is initiated and when the queue flush is completed and the
queue is now in normal operation.
MTB CELL FLUSH—0xD4 to 0xD7 MTBCF3 to MTBCF0
Table 87. MTBCF3–MTBCF0
7
MTBCF3
0xD4
Reserved
MTBCF2
0xD5
MTBCF2[7]
MTBCF1
0xD6
MTBCF1[7]
MTBCF0
0xD7
MTBCF0[7]
Type: Read/Write
6
MTBCF3[6]
MTBCF2[6]
MTBCF1[6]
MTBCF0[6]
5
MTBCF3[5]
MTBCF2[5]
MTBCF1[5]
MTBCF0[5]
4
MTBCF3[4]
MTBCF2[4]
MTBCF1[4]
MTBCF0[4]
3
MTBCF3[3]
MTBCF2[3]
MTBCF1[3]
MTBCF0[3]
2
MTBCF3[2]
MTBCF2[2]
MTBCF1[2]
MTBCF0[2]
1
MTBCF3[1]
MTBCF2[1]
MTBCF1[1]
MTBCF0[1]
0
MTBCF3[0]
MTBCF2[0]
MTBCF1[0]
MTBCF0[0]
Software Lock: Yes
Reset Value: 0x00
The MTBCF3, MTBCF2, MTBCF1 and MTBCF0 registers allow the PDU cell at the head of each of the queues
to be flushed. This removes the PDU cell from the head of the queue without corrupting the queue. The
processor sets the appropriate bit in the MTBCF register to flush a cell from a queue. When this has been
completed, the hardware will clear the bit. So after setting a bit to flush a cell from a queue, the processor should
poll the MTBCF register to determine when the flush has been completed.
• MTBCF3–MTBCF0 MTBCF3[6] corresponds to queue 31 and MTBCF0[0] corresponds to queue 0. When a
bit is set, then a flush of the PDU cell at the head of the queue is initiated and when clear, the cell flush is
completed and the queue is now in normal operation.
86
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