DS92UT16 Datasheet, PDF (74/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

DS92UT16
OBSOLETE
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
RECEIVE PORT B LOCAL ALARMS—0x62 RBLA
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Table 61. RBLA
7
6
5
Reserved RBLLC
RBLLM
Type: Bits[6:1] Read only/Clear on Read
Bit[0] Read/Write
4
RBLCS
3
2
RBLDSLL RBLTCLL
1
RBLFLL
0
ERBBF
Software Lock: No
Reset Value: 0x00
The Receive Port B Local Alarms register contains information on the status of the Port B disassembler. When
set, RBLLC, RBLLM, RBLDSLL, RBLTCLL, and RBLFLL will raise an interrupt if the corresponding interrupt
enable bits are set. Also, a change in value on RBLDSLL, RBLTCLL and RBLFLL will set the RBLCS bit, which
will raise an interrupt if the corresponding interrupt enable bit is set.
• RBLLC Receive Port B, Local Link Label Change of Status. Set = Change in RBLL register value.
• RBLLM Receive Port B, Local Link Label Mismatch. Set = Received link label RBLL different than expected
link label RBELL.
• RBLCS Receive Port B, Local Change of Status. Set = change in value of RBLDSLL, RBLTCLL or RBLFLL
bits.
• RBLDSLL Receive Port B, Local Descrambler Loss of Lock. Set = Out of Lock and Clear = Lock.
• RBLTCLL Receive Port B, Local Transport Container Delineation Loss of Lock. Set = Out of Lock and Clear
= Lock.
• RBLFLL Receive Port B, Local Frame Delineation Loss of Lock. Set = Out of Lock and Clear = Lock.
The ERBBF register bit indicates that the ECC receive section for Port B has successfully received a full ECC
message consisting of the 8 data bytes contained in registers ERBD7–ERBD0 and a the message can now be
read by the processor.
On reset, the ERBBF will be clear indicating no valid message has been received. When a valid message is
received and stored in the ERBD7–ERBD0 data registers, the ERBBF bit will be set and will raise an interrupt if
the corresponding interrupt enable bit is set. Therefore, the processor can detect a received message on the
interrupt or by polling the ERBBF bit. When the processor has finished reading the message from the
ERBD7–ERBD0 data registers and is ready to receive a new message, it simply clears the ERBBF bit. When a
full message has been successfully received, this is communicated to the far-end device via the ECC signaling.
• ERBBF The ERBBF bit, when set, indicates that ERBD7–ERBD0 data registers contain a full valid received
message. The data in the ERBD7–ERBD0 data registers cannot be overwritten with a new received message
while ERBBF is set. When ERBBF is cleared, this allows the ERBD7–ERBD0 data registers to be overwritten
with a new received message.
RECEIVE PORT B LOCAL INTERRUPT ENABLES—0x63 RBLIE
Table 62. RBLIE
7
Reserved
Type: Read/Write
6
RBLLCIE
5
RBLLMIE
4
RBLCSIE
3
RBLSLLIE
2
RBLTCLLI
E
1
RBLFLLIE
0
ERBBFIE
Software Lock: No
Reset Value: 0x00
This register contains the interrupt enables for the alarms in the RBLA register. Set = interrupt enabled and Clear
= interrupt disabled.
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