DS92UT16 Datasheet, PDF (66/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

DS92UT16
OBSOLETE
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
RECEIVE PORT A LOCAL INTERRUPT ENABLES—0x23 RALIE
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Table 43. RALIE
7
Reserved
Type: Read/Write
6
RALLCIE
5
RALLMIE
4
RALCSIE
3
RALDSLLI
E
2
RALTCLLI
E
1
RALFLLIE
0
ERABFIE
Software Lock: No
Reset Value: 0x00
This register contains the interrupt enables for the alarms in the RALA register. Set = interrupt enabled and Clear
= interrupt disabled.
RECEIVE PORT A CONTROL—0x24 RACTL
Table 44. RACTL
7
Reserved
Type: Read/Write
6
Reserved
5
Reserved
4
Reserved
3
RAESS
2
RABEC
1
RADFLK
0
RACDIS
Software Lock: Yes
Reset Value: 0x01
The Receive Port A Control register defines the operation of the Port A TCS DisAssembler section.
• RAESS Receive Port A, Valid Received ESS bit select. Two ESS bits are received in the Remote Alarm and
Signaling Byte as described in Remote Alarm and Signaling Byte. Only one of these received bits may be
designated as valid. The valid bit is extracted and passed to the ECC transmit section as the ECC signaling
bit (ESS) received on Port A. When RAESS is set then the Remote Alarm and Signaling Byte bit[1], ESSB, is
selected as valid and bit[2], ESSA is ignored. When RAESS is clear then the Remote Alarm and Signaling
Byte bit[2], ESSA, is selected as valid and bit[1], ESSB is ignored. The names ESSA and ESSB of these bits
refers to the remote receiver port from which they originated and are not associated with the local receivers
Port A and Port B. See Embedded Communication Channel Operation.
• RABEC Receive Port A, Bit Error Count mode. When set the receiver expects to receive the raw scrambler
PRBS pattern. See TXPRBS bit of the TERRCTL register. The descrambler will lock to this sequence and
then count individual bit errors in the PRBS stream. This bit error count will be refiected in the
RABEC2–RABEC0 registers. As there is no data cell delineation, the frame delineation will be lost. This is not
a live traffic test.
• RADFLK Receive Port A, Descrambler Force Lock. When set the descrambler will be forced out of lock and
will immediately begin to re-lock. The hardware will clear this bit and the descrambler lock status can be
monitored on the RALDSLL bit of the RALA register, see RECEIVE PORT A LOCAL ALARMS —0x22 RALA.
• RACDIS Receive Port A, Cell Discard. When set then cells with an errored HEC are discarded.
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