DS92UT16 Datasheet, PDF (73/111 Pages) Texas Instruments – DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

OBSOLETE
DS92UT16
www.ti.com
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
RECEIVE PORT A BIT ERROR COUNT—0x43 to 0x45 RABEC2 to RABEC0
Table 58. RABEC2–RABEC0
7
6
RABEC2
0x43
RABEC2[7] RABEC2[6]
RABEC1
0x44
RABEC1[7] RABEC1[6]
RABEC0
0x45
RABEC0[7] RABEC0[6]
Type: Read only/Clear on Read
5
RABEC2[5]
RABEC1[5]
RABEC0[5]
4
RABEC2[4]
RABEC1[4]
RABEC0[4]
3
RABEC2[3]
RABEC1[3]
RABEC0[3]
2
RABEC2[2]
RABEC1[2]
RABEC0[2]
1
RABEC2[1]
RABEC1[1]
RABEC0[1]
0
RABEC2[0]
RABEC1[0]
RABEC0[0]
Software Lock: No
Reset Value: 0x00
The RABEC2, RABEC1 and RABEC0 registers contain the Port A received bit error count whenever the RABEC
bit of the RACTL register is set. If the RABEC bit of the RACTL register is clear these registers are cleared.
• RABEC2–RABEC0 This register must be read in the order of most significant byte RABEC2 first and least
significant byte RABEC0 last, or the value read will not be valid. This counter will not roll-over from 0xFFFFFF
to 0x000000 but will stick at 0xFFFFFF.
RECEIVE PORT B LINK LABEL—0x60 RBLL
Table 59. RBLL
7
RBLL[7]
Type: Read only
6
RBLL[6]
5
RBLL[5]
4
RBLL[4]
3
RBLL[3]
2
RBLL[2]
1
RBLL[1]
0
RBLL[0]
Software Lock: No
Reset Value: 0x00
The Receive Port B Link Label register contains the Link Trace Label byte received in TC6 on receive Port B.
Whenever the received link label changes value, the RBLLC alarm bit in the RBLA register is set, which will raise
an interrupt if the corresponding interrupt enable bit is set.
• RBLL[7:0] Port B Received Link Trace Label byte contents.
RECEIVE PORT B EXPECTED LINK LABEL—0x61 RBELL
Table 60. RBELL
7
RBELL[7]
Type: Read/Write
6
RBELL[6]
5
RBELL[5]
4
RBELL[4]
3
RBELL[3]
2
RBELL[2]
1
RBELL[1]
0
RBELL[0]
Software Lock: No
Reset Value: 0x00
The Receive Port B Expected Link Label register defines the expected contents of the Link Trace Label byte
received in TC6 on receive Port B. If the actual received value, as stored in the RBLL register is not the same as
the expected value defined here the RBLLM alarm bit in the RBLA register is set, which may raise a processor
interrupt if the corresponding interrupt enable is set.
• RBELL[7:0] Port B Expected Received Link Trace Label byte contents.
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: DS92UT16
Submit Documentation Feedback
73