HD6413002 Datasheet, PDF (85/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

4.3 Interrupts
Interrupt exception handling can be requested by seven external sources (NMI, IRQ₀ to IRQ₅) and
30 internal sources in the on-chip supporting modules. Figure 4-4 classifies the interrupt sources
and indicates the number of interrupts of each type.
The on-chip supporting modules that can request interrupts are the watchdog timer (WDT),
refresh controller, 16-bit integrated timer-pulse unit (ITU), DMA controller (DMAC), serial
communication interface (SCI), and A/D converter. Each interrupt source has a separate vector
address.
NMI is the highest-priority interrupt and is always accepted. Interrupts are controlled by the
interrupt controller. The interrupt controller can assign interrupts other than NMI to two priority
levels, and arbitrate between simultaneous interrupts. Interrupt priorities are assigned in interrupt
priority registers A and B (IPRA and IPRB) in the interrupt controller.
For details on interrupts see section 5, Interrupt Controller.
Interrupts
External interrupts
NMI (1)
IRQ₀ to IRQ₅ (6)
Internal interrupts
WDT^*1 (1)
Refresh controller ^*2 (1)
ITU (15)
DMAC (4)
SCI (8)
A/D converter (1)
Notes: Numbers in parentheses are the number of interrupt sources.
1. When the watchdog timer is used as an interval timer, it generates an interrupt
request at every counter overflow.
2. When the refresh controller is used as an interval timer, it generates an interrupt
request at compare match.
Figure 4-4 Interrupt Sources and Number of Interrupts
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