HD6413002 Datasheet, PDF (168/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

Read cycle
Write cycle*
Refresh cycle
ø
Address
bus
CS ₃
(RAS )
HWR
(UCAS )
LWR
(LCAS )
RD
(WE)
RFSH
Row
Column
Row
Column
Area 3 top address
AS
Note: * 16-bit access
Figure 7-5 DRAM Control Signal Output Timing (1) (2WE Mode)
Figure 7-5 DRAM Control Signal Output Timing (2) (2CAS Mode)
Refresh Cycle Priority Order: When there are simultaneous bus requests, the priority order is:
(High) External bus master > refresh controller > DMA controller > CPU (Low)
For details see section 6.3.7, Bus Arbiter Operation.
Wait State Insertion: When bit AST3 is set to 1 in ASTCR, bus controller settings can cause
wait states to be inserted into bus cycles and refresh cycles. For details see section 6.3.5, Wait
Modes.
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