HD6413002 Datasheet, PDF (17/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

Table 1-1 Features (cont)
Feature
Memory
Interrupt
controller
Bus controller
Refresh
controller
DMA controller
(DMAC)
Description
RAM: 512 bytes
• Seven external interrupt pins: NMI, IRQ₀ to IRQ₅
• 30 internal interrupts
• Three selectable interrupt priority levels
• Address space can be partitioned into eight areas, with independent bus
specifications in each area
• Chip select output available for areas 0 to 3
• 8-bit access or 16-bit access selectable for each area
• Two-state or three-state access selectable for each area
• Selection of four wait modes
• Bus arbitration function
DRAM refresh
• Directly connectable to 16-bit-wide DRAM
• CAS-before-RAS refresh
• Self-refresh mode selectable
Pseudo-static RAM refresh
• Self-refresh mode selectable
Usable as an interval timer
Short address mode
• Maximum four channels available
• Selection of I/O mode, idle mode, or repeat mode
• Can be activated by compare match/input capture A interrupts from ITU
channels 0 to 3, SCI transmit-data-empty and receive-data-full interrupts, or
external requests
Full address mode
• Maximum two channels available
• Selection of normal mode or block transfer mode
• Can be activated by compare match/input capture A interrupts from ITU
channels 0 to 3, external requests, or auto-request
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