HD6413002 Datasheet, PDF (274/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

Port A Data Direction Register (PADDR): PADDR is an 8-bit write-only register that can select
input or output for each pin in port A.
Bit
Initial value
Read/Write
7
PA ₇
0
R/W
6
PA ₆
0
R/W
5
PA ₅
0
R/W
4
PA ₄
0
R/W
3
PA ₃
0
R/W
2
PA ₂
0
R/W
1
PA ₁
0
R/W
0
PA ₀
0
R/W
Port A data direction 7 to 0
These bits select input or output for port A pins
A pin in port A becomes an output pin if the corresponding PADDR bit is set to 1, and an input
pin if this bit is cleared to 0. In modes 3and 4, PA₇ functions as an address output pin regardless of
the PA7DDR setting.
PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PADDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting. If a PADDR bit is set to 1, the corresponding pin maintains its output
state in software standby mode.
Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores data for
pins PA₇ to PA₀.
Bit
Initial value
Read/Write
7
PA ₇
0
R/W
6
PA ₆
0
R/W
5
PA ₅
0
R/W
4
PA ₄
0
R/W
3
PA ₃
0
R/W
2
PA ₂
0
R/W
1
PA ₁
0
R/W
0
PA ₀
0
R/W
Port A data 7 to 0
These bits store data for port A pins
When a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is
returned directly. When a bit in PADDR is cleared to 0, if port A is read the corresponding pin
level is read.
PADR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
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