HD6413002 Datasheet, PDF (252/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

8.6.7 Memory and I/O Address Register Values
Table 8-14 indicates the address ranges that can be specified in the memory and I/O address
registers (MAR and IOAR).
Table 8-14 Address Ranges Specifiable in MAR and IOAR
MAR
IOAR
1-Mbyte Mode
H'00000 to H'FFFFF
(0 to 1048575)
H'FFF00 to H'FFFFF
(1048320 to 1048575)
16-Mbyte Mode
H'000000 to H'FFFFFF
(0 to 16777215)
H'FFFF00 to H'FFFFFF
(16776960 to 16777215)
Note: MAR bits 23 to 20 are ignored in 1-Mbyte mode.
8.6.8 Bus Cycle when Transfer is Aborted
When a transfer is aborted by clearing the DTE bit or suspended by an NMI that clears the DTME
bit, if this halts a channel for which the DMAC has a transfer request pending internally, a dead
cycle may occur. This dead cycle does not update the halted channel’s address register or counter
value. Figure 8-27 shows an example in which an auto-requested transfer in cycle-steal mode on
channel 0 is aborted by clearing the DTE bit in channel 0.
CPU cycle
DMAC cycle
CPU cycle
DMAC
cycle
CPU cycle
T₁ T₂ T_d T₁ T₂ T₁ T₂ T₁ T₂ T₃ T_d T_d T₁ T₂
ø
Address bus
RD
HWR, LWR
DTE bit is
cleared
Figure 8-27 Bus Timing at Abort of DMA Transfer in Cycle-Steal Mode
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