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| HD6413002 Datasheet, PDF (171/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller | |||
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Operation in Power-Down State: The refresh controller operates in sleep mode. It does not
operate in hardware standby mode. In software standby mode RTCNT is initialized, but RFSHCR,
RTMCSR bits 5 to 3, and RTCOR retain their settings prior to the transition to software standby
mode.
Example 1: Connection to 2WE 1-Mbit DRAM (1-Mbyte Mode): Figure 7-7 shows typical
interconnections to a 2WE 1-Mbit DRAM, and the corresponding address map. Figure 7-8 shows
a setup procedure to be followed by a program for this example. After power-up the DRAM must
be refreshed to initialize its internal state. Initialization takes a certain length of time, which can be
measured by using an interrupt from another timer module, or by counting the number of times
RTMCSR bit 7 (CMF) is set. Note that no refresh cycle is executed for the first refresh request
after exit from the reset state or standby mode (the first time the CMF flag is set; see figure 7-3).
When using this example, check the DRAM device characteristics carefully and use a procedure
that fits them.
H8/3002
A8
A7
A6
A5
A4
A3
A2
A1
2 WE 1-Mbit DRAM with
à 16-bit organization
A7
A6
A5
A4
A3
A2
A1
A0
CS 3
RD
HWR
LWR
D15 to D 0
RAS
CAS
UW
LW
OE
I/O15 to I/O 0
a. Interconnections (example)
H'60000
H'7FFFF
DRAM area
Area 3 (1-Mbyte mode)
b. Address map
156
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