HD6413002 Datasheet, PDF (133/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

16-Bit, Three-State-Access Areas: Figures 6-6 to 6-8 show the timing of bus control signals for a
16-bit, three-state-access area. In these areas, the upper address bus (D₁₅ to D₈) is used to access
even addresses and the lower address bus (D₇ to D₀) is used to access odd addresses. Wait states
can be inserted.
Bus cycle
T₁
T₂
T₃
ø
Address bus
CS_n
Even external address in area n
AS
RD
Read
access
D₁₅ to D₈
D₇ to D ₀
HWR
Valid
Invalid
Write
access
LWR
D₁₅ to D₈
High
D₇ to D ₀
Note: n = 7 to 0 (but for CS_n, n = 3 to 0)
Valid
Undetermined data
Figure 6-6 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (1)
(Byte Access to Even Address)
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