HD6413002 Datasheet, PDF (125/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

6.2.5 Bus Release Control Register (BRCR)
BRCR is an 8-bit readable/writable register that enables address output on bus lines A₂₃ to A₂₁
and enables or disables release of the bus to an external device.
Bit
7
6
5
4
3
2
1
0
A23E A22E A21E
—
—
—
—
BRLE
Initial value
1
1
1
1
1
1
1
0
Read/ ^{Modes 1, 2 —}
—
—
—
—
—
—
R/W
Write _{Modes 3, 4 R/W}
R/W
R/W
—
—
—
—
R/W
Address 23 to 21 enable
These bits enable PA ₆ to
PA ₄ to be used for A ₂₃ to
A₂₁ address output
Reserved bits
Bus release enable
Enables or disables
release of the bus
to an external device
BRCR is initialized to H'FE by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Address 23 Enable (A23E): Enables PA₄ to be used as the A₂₃ address output pin.
Writing 0 in this bit enables A₂₃ address output from PA₄. In modes other than 3 and 4 this bit
cannot be modified and PA₄ has its ordinary input/output functions.
Bit 7
A23E
0
1
Description
PA₄ is the A₂₃ address output pin
PA₄ is the PA₄/TP₄/TIOCA₁ input/output pin
(Initial value)
110