HD6413002 Datasheet, PDF (491/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

Restrictions on Usage of DMAC
To have the DMAC read RDR, be sure to select the SCI receive-data-full interrupt (RXI) as the
activation source with bits DTS2 to DTS0 in DTCR.
Restrictions in Synchronous Mode: When data transmission is performed using an external
clock source as the serial clock, an interval of at least 5 states is necessary between clearing the
TDRE bit in SSR and the start (falling edge) of the first transmit clock pulse corresponding to
each frame (figure 13-22). This interval is also necessary when performing continuous
transmission. If this condition is not satisfied, an operation error may occur.
SCK
t*
t*
TDRE
TXD
X0 X1 X2 X3 X4 X5 X6 X7 Y0 Y1 Y2 Y3
Note: * Make sure that t is at least 5 states.
Continuous transmission
Figure 13-22 Transmission in Synchronous Mode (Example)
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