HD6413002 Datasheet, PDF (693/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

Table D-1 Port States (cont)
Pin
Name
Mode
Reset
State
Hardware Software
Standby Standby
Mode
Mode
Bus-
Released
Mode
Program
Execution
Sleep Mode
P8₀
1 to 4
T
T
(RFSHE = 0)
keep
(RFSHE = 1)
RFSH
(RFSHE = 0)
keep
(RFSHE = 1)
H
I/O port
(RFSHE = 0)
or RFSH
(RFSHE = 1)
P8₃ to P8₁ 1 to 4
T
T
(DDR = 0)
T
(DDR = 1)
H
keep
Input port
(DDR = 0) or
CS₃ to CS₁
(DDR = 1)
P8₄
1 to 4
L
T
(DDR = 0)
T
(DDR = 1)
L
keep
Input port
(DDR = 0)
or CS₀
(DDR = 1)
P9₅ to P9₀
PA₃ to PA₀
PA₆ to PA₄
1 to 4
1 to 4
1, 2
3, 4
T
T
T
T
T
T
T
T
keep
keep
keep
I/O port^*1
keep
keep
keep
I/O port^*2
I/O port
I/O port
I/O port
A₂₃, A₂₂, A₂₁
(A23E/A22E/
A21E = 0)
or I/O port
(A23E/A22E/
A21E = 1)
PA₇
1, 2
3, 4
T
T
T
T
keep
I/O port^*1
keep
I/O port^*2
I/O port
A
20
PB₇ to PB₀ 1 to 4
T
T
keep
keep
I/O port
Notes: 1. The pin state depends on the DDR bit.
2. The pin state depends on the ITU output enable and DDR bits.
Legend
H: High
L: Low
T: High-impedance state
keep: Input pins are in the high-impedance state; output pins maintain their previous state.
DDR: Data direction register bit
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