HD6413002 Datasheet, PDF (696/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

Reset in T₃ State: Figure D-3 is a timing diagram for the case in which RES goes low during the
T₃ state of an external memory access cycle. As soon as RES goes low, all ports are initialized to
the input state. AS, RD, HWR, and LWR go high, and the data bus goes to the high-impedance
state. The address bus outputs are held during the T₃ state.The same timing applies when a reset
occurs in the T₂ state of an access cycle to a two-state-access area.
Access to external address
T₁
T₂
T₃
ø
RES
Internal
reset signal
Address bus
H'000000
CS₀
CS₃ to CS₁
AS
High impedance
RD (read access)
HWR, LWR
(write access)
Data bus
(write access)
I/O port
High impedance
High impedance
Figure D-3 Reset during Memory Access (Reset during T₃ State)
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